[aarch64-port-dev ] 64-Bit literal oops

[Stuart Monteith]

Hello,
   As requested, I've gotten what is appears to be near the minimal
set of changes for 64-bit literal oops. We really only need this for
ZGC, so apart from testing, it would only be ZGC enabling it.
Otherwise, there are no other interesting uses, apart from maybe as
support for 52-bit addressing.


I've tested with movz, movk, movk, possible movk patching in
MacroAssembler::pd_patch_instruction_size and
MacroAssembler::target_addr_for_insn . The "ShouldNotReachHere()"
calls are never tripped, and so could be taken out.

I'm pushing down a flag from movoop down to movptr, to indicate when
an oop literal is being emitted, which movoop obviously implicitly
knows:
    MacroAssembler::movoop(Register, jobject, bool)
    MacroAssembler:mov(Register, Address, bool isOop)
    MacroAssembler:movptr(Register, u_int64_t, bool isOop)

NativeMovConstReg has been changed to detect the size of the
instruction - as it may be a movz,movk,movk combination, or perhaps it
will be an oop with an additional movk for the 64-bit literal oop. It
does this conditionally. I have been considering adding an additional
check by comparing the register being stored to.

I'm looking now at adding information to relocs to indicate they are
for an oop, as suggested by aph.


BR,
   Stuart