[aarch64-port-dev ] RFR(M): 8209835: Aarch64: elide barriers on all volatile operations

[Andrew Haley]

On 10/16/2018 09:27 AM, Andrew Haley wrote:
> On 10/15/2018 04:57 PM, Andrew Haley wrote:
>> Andrew Dinn wrote:
>>
>>> I didn't eyeball the code (there's a lot to check!). I extended tests to
>>> cover all combination of atomic operations/argument types. So at least,
>>> tests should guarantee that the right variant in the ad file is
>>> picked. Then, of course, all variants must be correctly implemented. For
>>> that, I checked a couple times that the right boolean flag was passed.
> 
> I tested on a ThunderX2 machine with the LSE instruction set, and the
> jtreg tests all pass. I'll do a jcstress test on that box too, just to
> be sure.

This is what we need for LSE. I'm running jcstress again.

-- 
Andrew Haley
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671
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diff -r c64384f414bc src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
--- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp	Wed Oct 10 23:05:15 2018 +0200
+++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp	Tue Oct 16 12:57:56 2018 -0400
@@ -2367,21 +2367,18 @@
                              bool weak,
                              Register result) {
   if (result == noreg)  result = rscratch1;
+  BLOCK_COMMENT("cmpxchg {");
   if (UseLSE) {
     mov(result, expected);
     lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
-    cmp(result, expected);
+    compare_eq(result, expected, size);
   } else {
-    BLOCK_COMMENT("cmpxchg {");
     Label retry_load, done;
     if ((VM_Version::features() & VM_Version::CPU_STXR_PREFETCH))
       prfm(Address(addr), PSTL1STRM);
     bind(retry_load);
     load_exclusive(result, addr, size, acquire);
-    if (size == xword)
-      cmp(result, expected);
-    else
-      cmpw(result, expected);
+    compare_eq(result, expected, size);
     br(Assembler::NE, done);
     store_exclusive(rscratch1, new_val, addr, size, release);
     if (weak) {
@@ -2390,9 +2387,27 @@
       cbnzw(rscratch1, retry_load);
     }
     bind(done);
-    BLOCK_COMMENT("} cmpxchg");
   }
-}
+  BLOCK_COMMENT("} cmpxchg");
+}
+
+// A generic comparison. Only compares for equality, clobbers rscratch1.
+void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
+  if (size == xword) {
+    cmp(rm, rn);
+  } else if (size == word) {
+    cmpw(rm, rn);
+  } else if (size == halfword) {
+    eorw(rscratch1, rm, rn);
+    ands(zr, rscratch1, 0xffff);
+  } else if (size == byte) {
+    eorw(rscratch1, rm, rn);
+    ands(zr, rscratch1, 0xff);
+  } else {
+    ShouldNotReachHere();
+  }
+}
+
 
 static bool different(Register a, RegisterOrConstant b, Register c) {
   if (b.is_constant())
diff -r c64384f414bc src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp
--- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp	Wed Oct 10 23:05:15 2018 +0200
+++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp	Tue Oct 16 12:57:56 2018 -0400
@@ -1020,7 +1020,10 @@
                enum operand_size size,
                bool acquire, bool release, bool weak,
                Register result);
+private:
+  void compare_eq(Register rn, Register rm, enum operand_size size);
 
+public:
   // Calls
 
   address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);