[aarch64-port-dev ] RFR: [8u] 8209835: Aarch64: elide barriers on all volatile operations

[Yangfei (Felix)]

On 8/28/19 10:18 AM, Yangfei (Felix) wrote:

>> Well, I think I won't be able to provide such a test case after some 
>> throughts.  Now I agree that this will not affect basic functionality.  
>> As we have handled unsafe.compareAndSwap, I don't see a reason to not 
>> handle unsafe.getAndSet: the risk should be low and we get consistent 
>> and improved C2 JIT code.  What do you think?

> I think that's a powerful argument for the development code because it's an improvement; conversely I don't think it's an argument for a backport.

> Having said that, I can sort-of imagine a jcstress failure if we had a test that was doing compareAndSwap in one thread and getAndSet in another. That would be a seriously compelling reason for a backport!

Can you elaborate more please? especially the possible code sequence. 

Currently, we have C2 JIT for getAndSet like this: 

 33   ;; membar_release
 34   0x0000ffffa416ae74: dmb       ish
 35   ;; 0x40000000000
 36   0x0000ffffa416ae78: orr       x11, xzr, #0x40000000000
 37   0x0000ffffa416ae7c: add       x10, x1, #0x10
 38   0x0000ffffa416ae80: prfm      pstl1strm, [x10]
 39   0x0000ffffa416ae84: ldxr      x9, [x10]
 40   0x0000ffffa416ae88: stxr      w8, x11, [x10]
 41   0x0000ffffa416ae8c: cbnz      w8, 0x0000ffffa416ae84
 42   0x0000ffffa416ae90: mov       x10, x9
 43   ;; membar_acquire
 44   0x0000ffffa416ae94: dmb       ishld           ;*invokevirtual getAndSetLong

I think the two dmb instructions at the head and tail should ensure the consistency.  Isn't it? 

> It would be interesting to see such a jcstress test. Even if the test does not fail, we could look at the generated code to see if it might fail according to the Arm memory model.