[aarch64-port-dev ] RFR: 8222412 - AARCH64: multiple instructions encoding issues

[Dmitrij Pochepko]

Hi all,

please review patch for JDK-8222412 - AARCH64: multiple instructions 
encoding issues

I updated python script aarch64-asmtest.py used for automatic tests 
generation and requesting review for the issues found by eyeballing and 
by the updated script.

Issue: https://bugs.openjdk.java.net/browse/JDK-8222412

Webrev of instruction encoding cumulative fix: 
http://cr.openjdk.java.net/~dpochepk/8222412/webrev.02/ 
(assembler_aarch64.cpp part consists of automatically generated 
instructions only).

Updated script: 
http://cr.openjdk.java.net/~dpochepk/8222412/webrev.02/aarch64-asmtest.py

Fixes summary:

incorrect encoding fixes:
- post_reg addressing mode is encoded incorrectly in case of r0 index 
register (caused by declaration of r0 as 0 i.e. NULL). Fixed. Testcase 
is generated by aarch64-asmtest.py.
- load-with-replicate instructions (ld1r, ld2r, ld3r, ld4r) with post 
immediate addressing mode are encoded incorrectly (offset value should 
be calculated differently for replicate and non-replicate instructions). 
Fixed. Testcase is generated by aarch64-asmtest.py.
- ld1*/ld2*/ld3*/ld4* instructions should accept subsequent SIMD 
registers modulo 32. (i.e. "v31, v0, v1, v2" is valid sequence). Current 
implementation is not calculating modulo 32. Fixed. Testcase is 
generated by aarch64-asmtest.py.

missing asserts fixes:
- bitfield move instructions (*bfm*) accept out-of-range parameters for 
32-bit version. Check added.
- extrw instruction encoding accept out-of-range parameter. Check added.
- logical operations(and, orr, eor, bic, orn, eon) with shifted register 
accept out-of-range parameter for 32-bit versions. Check added.
- add, sub instructions with shifted register accept out-of-range 
parameter for 32-bit versions. Check added.
- vector versions of add, sub, mul, mla, mls, sshl, ushl, umull, umlal 
accept incorrect simd type. Check added.
- vector versions of abs, neg, not, add, cls, clz, cnt, uaddl accept 
incorrect simd type. Check added.
- vector instructions with immediate argument (mov, orr, mvn, bic) 
accept incorrect shift value and silently convert it. Check added.
- simd move to general purpose register allows incorrect simd 
arrangement type. Check added.
- zip/uzp/trn instructions accept incorrect simd arrangement type. Check 
added.


zero register fixes:
- extr and extrw encoding do not allow zr as parameter. Fixed. Testcase 
is generated by aarch64-asmtest.py.
- pair exclusive load/store instructions doesn't allow 2nd target 
register to be zr (while allowing 1st). Fixed. Testcase is generated by 
aarch64-asmtest.py.
- lse atomic instructions doesn't allow source register to be zr (for 
example, no swap (swp) with zr is allowed). Fixed. Testcase is generated 
by aarch64-asmtest.py.
- conditional compare instructions doesn't allow 1st compared register 
to be zr. Fixed. Testcase is generated by aarch64-asmtest.py.
- simd move from general purpose register doesn't allow to use zero 
register as source. Fixed. Testcase is generated by aarch64-asmtest.py.
- simd dup instruction doesn't allow to use zero register as duplication 
source. Fixed. Testcase is generated by aarch64-asmtest.py.

miscellaneous fixes:

- ushll and ushll2 instructions are implemented as synonyms. Same with 
pmull/pmull2. Fixed.
- fixed assert message misprint in add,sub instructions with extended 
register


Testing:
I checked instructions generation via python-generated code in release 
and fastdebug build.
I also run hotspot jtreg tests: compiler/*, gc/* and runtime/* using 
fastdebug build.

Thanks,
Dmitrij