[aarch64-port-dev ] RFR: aarch64: minor improvements of atomic operations

[Andrew Dinn]

On 12/11/2019 09:25, Andrew Haley wrote:
> On 11/12/19 8:37 AM, Yangfei (Felix) wrote:
>> This has been discussed somewhere before: https://patchwork.kernel.org/patch/3575821/ 
>> Let's keep the current status for safe.  
> 
> Yes.
> 
> It's been interesting to see the progress of this patch. I don't think
> it's the first time that someone has been tempted to change this code
> to make it "more efficient".
> 
> I wonder if we could perhaps add a comment to that code so that it
> doesn't happen again. I'm not sure exactly what the patch should say
> beyond "do not touch". Perhaps something along the lines of "Do not
> touch this code unless you have at least Black Belt, 4th Dan in memory
> ordering."  :-)
> 
> More seriously, maybe simply "Note that memory_order_conservative
> requires a full barrier after atomic stores. See
> https://patchwork.kernel.org/patch/3575821/"
Yes, that would be a help. It's particularly easy to get confused here
because we happily omit the ordering of an stlr store wrt subsequent
stores when the strl is implementing a Java volatile write or a Java
cmpxchg.

So, it might be worth adding a rider that implementing the full
memory_order_conservative semantics is necessary because VM code relies
on the strong ordering wrt writes that the cmpxchg is required to provide.

regards,


Andrew Dinn
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