[aarch64-port-dev ] RFR: [8u] 8209835: Aarch64: elide barriers on all volatile operations
Yangfei (Felix)
felix.yang at huawei.com
Tue Oct 29 10:04:24 UTC 2019
Actually, I didn't see a real world problem related to this.
As you mentioned before, there should be a StoreLoad barrier between a volatile store and a volatile load.
I agree with that and I didn't see this kind of barrier when we have a getAndSet followed by a CompareAndSwap.
I just worried that developers may create code that relies on this memory model requirement.
Currently we have C2 JIT for getAndSetLong like:
33 ;; membar_release
34 0x0000ffffa416ae74: dmb ish
35 ;; 0x40000000000
36 0x0000ffffa416ae78: orr x11, xzr, #0x40000000000
37 0x0000ffffa416ae7c: add x10, x1, #0x10
38 0x0000ffffa416ae80: prfm pstl1strm, [x10]
39 0x0000ffffa416ae84: ldxr x9, [x10]
40 0x0000ffffa416ae88: stxr w8, x11, [x10] <========
41 0x0000ffffa416ae8c: cbnz w8, 0x0000ffffa416ae84 <========
42 0x0000ffffa416ae90: mov x10, x9
43 ;; membar_acquire
44 0x0000ffffa416ae94: dmb ishld ;*invokevirtual getAndSetLong
And C2 JIT for compareAndSwapLong like:
433 0x0000ffffa6695088: ldaxr x8, [x10]
434 0x0000ffffa669508c: cmp x8, x3
435 0x0000ffffa6695090: b.ne 0x0000ffffa669509c
436 0x0000ffffa6695094: stlxr w8, x4, [x10]
437 0x0000ffffa6695098: cbnz w8, 0x0000ffffa6695088
438 0x0000ffffa669509c: cset x0, eq ;*invokevirtual compareAndSwapLong
Thanks,
Felix
>
> On 10/28/19 6:11 AM, Yangfei (Felix) wrote:
> > Ping...
> > Is that enough for us to push the 8u backport patch ?
> > It still applies:
> > http://cr.openjdk.java.net/~fyang/8209835-8u-backport/webrev.00/
>
> Does this change fix any bugs?
>
> Does this change make a significant performance improvement?
>
> It is not a low-risk change and I'm not sure it's worth it.
> Andrew Dinn, what do you think?
>
> --
> Andrew Haley (he/him)
> Java Platform Lead Engineer
> Red Hat UK Ltd. <https://www.redhat.com> https://keybase.io/andrewhaley
> EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671
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