[aarch64-port-dev ] RFR: [8u] 8209835: Aarch64: elide barriers on all volatile operations

[Yangfei (Felix)]

> On 10/31/19 3:03 AM, Yangfei (Felix) wrote:
> > My thoughts about the risk:
> >   Suppose we have T1 executing getAndSetLong on Core1 and T2 executing
> compareAndSwapLong on Core2.
> >   Consider execution order: T1 - > T2
> >   The stxr of the getAndSetLong sequence executed on T1/Core1 may not
> be observed by T2/Core2.
> >   The dmb ishld at the end of the getAndSetLong sequence does not ensure
> the visibility of the stxr, according to the architecture manual.
> 
> Is the case you are talking about to the same variable or to different variables?
> 
> If it's the same variable then the rules of multi-copy atomicity apply, and the
> stxr is definitely visible to a ldaxr. All stores, regardless of barrier instructions,
> are coherent. If it's a different variable then there is no happens-before
> relationship between them.

I am talking about the case when they operate on the same variable.  
Looks like I missed the details of the aarch64's Other-multi-copy atomicity.  
Thanks for the clarification.  

Felix