[aarch64-port-dev ] [15] RFR: 8248048: ZGC: AArch64: SIGILL in load barrier register spilling

[Andrew Haley]

On 26/06/2020 11:05, Andrew Dinn wrote:
> Yes, nice catch. zr is clearly the wrong choice here. In the context of
> an FP register it ends up being interpreted as q31 which, as you show,
> clashes when r31 is the last register in an odd register set.

OK.

I'm sure we've seen this bug years ago and fixed it. maybe the fix was
never pushed, or maybe it was another instance of the same error.

-- 
Andrew Haley  (he/him)
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
https://keybase.io/andrewhaley
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