[aarch64-port-dev ] Reply：Aarch64: CPU_Model support for Neoverse N1/N2/V1/V2

[Jin Guojie]

Hi Andrew,

On 2024/4/18  Andrew Haley wrote:

> On 4/18/24 03:29, Jin Guojie wrote:
>> We wrote a patch to improve the definition of CPU models for Arm Neoverse.

> Sure. My immediate reaction is that having separate categories for the Neoverse
> CPUs is getting to be rather cumbersome. Clearly they have a lot in common,
> and it would be nicer to be able to say things like
>    "if CPU is Arm.Neoverse" or "is Arm.Neoverse.V2"
> but right now I can't think of a nice way to do that. Maybe a nested class  hierarchy?

>> Could you please create an issue in the JDK Bug System (JBS),
> I will, but let's have some ideas about what the result should be.

We have re-optimized the code style of the Neoverse CPU model definition. 
To achieve higher compiler compatibility, we used simple judgment logic in vm_version_aarch64.hpp. 

We also analyzed vm_version_x86.hpp and did not find the "nested class hierarchy" syntax you mentioned. 
The way X86 uses to determine the CPU type is to define a set of is_xxx() functions, just like the style we use in the patch below.

The main program (vm_version_aarch64.cpp) looks more concise now. 

Looking forward to your suggestions. Thanks.

-- 
Jin Guojie(Alibaba, hotspot developer)


diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
index 18f310c746c..5fc2b5cee2d 100644
--- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
+++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp
@@ -212,13 +212,7 @@ void VM_Version::initialize() {
     }
   }
 
-  // Neoverse
-  //   N1: 0xd0c
-  //   N2: 0xd49
-  //   V1: 0xd40
-  //   V2: 0xd4f
-  if (_cpu == CPU_ARM && (model_is(0xd0c) || model_is(0xd49) ||
-                          model_is(0xd40) || model_is(0xd4f))) {
+  if (is_neoverse_family()) {
     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
     }
@@ -247,10 +241,7 @@ void VM_Version::initialize() {
     FLAG_SET_DEFAULT(UseCRC32, false);
   }
 
-  // Neoverse
-  //   V1: 0xd40
-  //   V2: 0xd4f
-  if (_cpu == CPU_ARM && (model_is(0xd40) || model_is(0xd4f))) {
+  if (is_neoverse_v_series()) {
     if (FLAG_IS_DEFAULT(UseCryptoPmullForCRC32)) {
       FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, true);
     }
diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp
index f6cac72804f..323b7e8e151 100644
--- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp
+++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp
@@ -114,6 +114,13 @@ enum Ampere_CPU_Model {
     CPU_MODEL_AMPERE_1B = 0xac5  /* AMPERE_1B core Implements ARMv8.7 with CSSC, MTE, SM3/SM4 extensions */
 };
 
+enum Neoverse_CPU_Model {
+    CPU_MODEL_NEOVERSE_N1 = 0xd0c,
+    CPU_MODEL_NEOVERSE_N2 = 0xd49,
+    CPU_MODEL_NEOVERSE_V1 = 0xd40,
+    CPU_MODEL_NEOVERSE_V2 = 0xd4f,
+};
+
 #define CPU_FEATURE_FLAGS(decl)               \
     decl(FP,            fp,            0)     \
     decl(ASIMD,         asimd,         1)     \
@@ -156,6 +163,22 @@ enum Ampere_CPU_Model {
     return _model == cpu_model || _model2 == cpu_model;
   }
 
+  static bool is_neoverse_family() {
+    return _cpu == CPU_ARM
+	  && (model_is(CPU_MODEL_NEOVERSE_N1) || model_is(CPU_MODEL_NEOVERSE_N2) ||
+              model_is(CPU_MODEL_NEOVERSE_V1) || model_is(CPU_MODEL_NEOVERSE_V2));
+  }
+
+  static bool is_neoverse_n_series() {
+    return is_neoverse_family() && 
+              (model_is(CPU_MODEL_NEOVERSE_N1) || model_is(CPU_MODEL_NEOVERSE_N2));
+  }
+
+  static bool is_neoverse_v_series() {
+    return is_neoverse_family() && 
+              (model_is(CPU_MODEL_NEOVERSE_V1) || model_is(CPU_MODEL_NEOVERSE_V2));
+  }
+
   static bool is_zva_enabled() { return 0 <= _zva_length; }
   static int zva_length() {
     assert(is_zva_enabled(), "ZVA not available");