RFR: 8346706: RISC-V: Add available registers to hs_err
Robbin Ehn
rehn at openjdk.org
Fri Dec 20 13:25:36 UTC 2024
On Fri, 20 Dec 2024 12:52:07 GMT, Magnus Ihse Bursie <ihse at openjdk.org> wrote:
>> Hi please consider.
>>
>> This adds below to hs_err:
>>
>> Floating point state:
>> fcsr=1
>> Floating point registers:
>> f0=0xffffffff44a72000 | 1.84467e+19
>> f1=0xffffffff44a72000 | 1.84467e+19
>> ....
>> f31=0xffffffff44a72000 | 1.84467e+19
>>
>> Vector state:
>> vstart=0x0000000000000000
>> vl=0x0000000000000020
>> vtype=0x0000000000000000
>> vcsr=0x0000000000000000
>> vlenb=0x0000000000000020
>> Vector registers:
>> v0=0x0101010101010101010101010101010101010101010101010101010101010101
>> ....
>> v31=0x0101010101010101010101010101010101010101010101010101010101010101
>>
>>
>> To get vector the headers need to include those structures, hence build files hackery.
>> This means if you compile on a kernel without RVV support the error handler will lack support for it.
>> We don't care about RVV option as carshing in native may still use vector even if the jit do not.
>>
>> I'm doubt full about the printing as double for fp regs, maybe that should be removed.
>>
>> Local testing, running t1 over weekend.
>>
>> Thanks, Robbin
>
> make/hotspot/lib/CompileJvm.gmk line 139:
>
>> 137:
>> 138: ifeq ($(call isTargetCpu, riscv64), true)
>> 139: JVM_CFLAGS += $(RVV_CFLAGS)
>
> The new flag should be added to the JVM_CFLAGS at configure time. No need to export it to spec.gmk and do it at runtime.
The flag is different for the build JVM and the JVM.
If I just set in configure time it seem like both OPENJDK_BUILD_JVM_CFLAGS and JVM_CFLAGS have the flag.
Which is incorrect, as only OPENJDK_BUILD_JVM_CFLAGS in this case should have it.
Am I doing something wrong? I mirrored SVE_FLAGS which do this...
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PR Review Comment: https://git.openjdk.org/jdk/pull/22845#discussion_r1893933496
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