RFR: 8346706: RISC-V: Add available registers to hs_err [v3]

[Robbin Ehn]

> Hi please consider.
> 
> This adds below to hs_err:
> 
> Floating point state:
> fcsr=1
> Floating point registers:
> f0=0xffffffff44a72000 | 1.84467e+19
> f1=0xffffffff44a72000 | 1.84467e+19
> ....
> f31=0xffffffff44a72000 | 1.84467e+19
> 
> Vector state:
> vstart=0x0000000000000000
> vl=0x0000000000000020
> vtype=0x0000000000000000
> vcsr=0x0000000000000000
> vlenb=0x0000000000000020
> Vector registers:
> v0=0x0101010101010101010101010101010101010101010101010101010101010101
> ....
> v31=0x0101010101010101010101010101010101010101010101010101010101010101
> 
> 
> To get vector the headers need to include those structures, hence build files hackery.
> This means if you compile on a kernel without RVV support the error handler will lack support for it.
> We don't care about RVV option as carshing in native may still use vector even if the jit do not.
> 
> I'm doubt full about the printing as double for fp regs, maybe that should be removed.
> 
> Local testing, running t1 over weekend.
> 
> Thanks, Robbin

Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains five additional commits since the last revision:

 - Merge branch 'master' into vregs
 - Review comments
 - Make file fixes
 - Fixed ws
 - Baseline

-------------

Changes:
  - all: https://git.openjdk.org/jdk/pull/22845/files
  - new: https://git.openjdk.org/jdk/pull/22845/files/49fe4086..5cb8c776

Webrevs:
 - full: https://webrevs.openjdk.org/?repo=jdk&pr=22845&range=02
 - incr: https://webrevs.openjdk.org/?repo=jdk&pr=22845&range=01-02

  Stats: 5792 lines in 140 files changed: 3927 ins; 1462 del; 403 mod
  Patch: https://git.openjdk.org/jdk/pull/22845.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/22845/head:pull/22845

PR: https://git.openjdk.org/jdk/pull/22845