RFR: 8346706: RISC-V: Add available registers to hs_err [v4]

[Robbin Ehn]

On Tue, 7 Jan 2025 13:07:03 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> Hi please consider.
>> 
>> This adds below to hs_err:
>> 
>> Floating point state:
>> fcsr=1
>> Floating point registers:
>> f0=0xffffffff44a72000 | 1.84467e+19
>> f1=0xffffffff44a72000 | 1.84467e+19
>> ....
>> f31=0xffffffff44a72000 | 1.84467e+19
>> 
>> Vector state:
>> vstart=0x0000000000000000
>> vl=0x0000000000000020
>> vtype=0x0000000000000000
>> vcsr=0x0000000000000000
>> vlenb=0x0000000000000020
>> Vector registers:
>> v0=0x0101010101010101010101010101010101010101010101010101010101010101
>> ....
>> v31=0x0101010101010101010101010101010101010101010101010101010101010101
>> 
>> 
>> To get vector the headers need to include those structures, hence build files hackery.
>> This means if you compile on a kernel without RVV support the error handler will lack support for it.
>> We don't care about RVV option as carshing in native may still use vector even if the jit do not.
>> 
>> I'm doubt full about the printing as double for fp regs, maybe that should be removed.
>> 
>> Local testing, running t1 over weekend.
>> 
>> Thanks, Robbin
>
> Robbin Ehn has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Review comments

Thanks!

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PR Comment: https://git.openjdk.org/jdk/pull/22845#issuecomment-2579903459