RFR: 8271515: Integration of JEP 417: Vector API (Third Incubator) [v2]

[Paul Sandoz]

On Thu, 14 Oct 2021 17:21:25 GMT, Paul Sandoz <psandoz at openjdk.org> wrote:

>> This PR improves the performance of vector operations that accept masks on architectures that support masking in hardware, specifically Intel AVX512 and ARM SVE.
>> 
>> On architectures that do not support masking in hardware the same technique as before is applied to most operations, specifically composition using blend.
>> 
>> Masked loads/stores are a special form of masked operation that require additional care to ensure out-of-bounds access throw exceptions. The range checking has not been fully optimized and will require further work.
>> 
>> No API enhancements were required and only a few additional tests were needed.
>
> Paul Sandoz has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Apply patch from https://github.com/openjdk/panama-vector/pull/152

@njian there is a conflict with `macroAssembler_aarch64.cpp`:


--- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
+++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
@@@ -2580,8 -2495,8 +2571,13 @@@ void MacroAssembler::pop_call_clobbered
  }
  
  void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
++<<<<<<< HEAD
 +                                    int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
 +  push(0x3fffffff, sp);         // integer registers except lr & sp
++=======
+                                     int sve_vector_size_in_bytes) {
+   push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
++>>>>>>> master
    if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
      sub(sp, sp, sve_vector_size_in_bytes * FloatRegisterImpl::number_of_registers);
      for (int i = 0; i < FloatRegisterImpl::number_of_registers; i++) {


I think the resolution is this:


@@ -2581,7 +2572,7 @@ void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
 
 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
                                     int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
-  push(0x3fffffff, sp);         // integer registers except lr & sp
+  push(RegSet::range(r0, r29), sp); // integer registers except lr & sp


is that correct?

-------------

PR: https://git.openjdk.java.net/jdk/pull/5873