RFR: 8289552: Make intrinsic conversions between bit representations of half precision values and floats

[Sandhya Viswanathan]

On Fri, 5 Aug 2022 16:36:23 GMT, Smita Kamath <svkamath at openjdk.org> wrote:

> 8289552: Make intrinsic conversions between bit representations of half precision values and floats

src/hotspot/cpu/x86/assembler_x86.cpp line 1927:

> 1925:   assert(VM_Version::supports_evex(), "");
> 1926:   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /*uses_vl */ true);
> 1927:   attributes.set_is_evex_instruction();

This instruction is supported on AVX (vex encoded) platform as well.
Please rename this as vcvtps2ph and update the check to include supports_evex or supports_f16C. The is_evex_instruction check should then be remvoed.

src/hotspot/cpu/x86/assembler_x86.cpp line 1931:

> 1929:   emit_int8((unsigned char)0x1D);
> 1930:   emit_int8((unsigned char)(0xC0 | encode));
> 1931:   emit_int8(imm8);

You could do emit_int24() here.

src/hotspot/cpu/x86/assembler_x86.cpp line 1937:

> 1935:   assert(VM_Version::supports_evex(), "");
> 1936:   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */false, /* no_mask_reg */ true, /* uses_vl */ true);
> 1937:   attributes.set_is_evex_instruction();

This instruction is supported on AVX (vex encoded) platform as well.
Please rename this as vcvtph2ps and update the check to include supports_evex or supports_f16C. The is_evex_instruction check should then be remvoed.

src/hotspot/cpu/x86/x86.ad line 1686:

> 1684:     case Op_ConvHF2F:
> 1685:       if (!VM_Version::supports_evex() || !VM_Version::supports_avx512vl()) {
> 1686:         return false;

Please include supports_f16c here.

src/hotspot/cpu/x86/x86_64.ad line 11310:

> 11308: 
> 11309: instruct convF2HF_reg_reg(rRegI dst, regF src, regF tmp) %{
> 11310:   predicate(VM_Version::supports_evex());

The predicate could be removed as the check is fully done in match_rule_supported.

src/hotspot/cpu/x86/x86_64.ad line 11313:

> 11311:   effect(TEMP tmp);
> 11312:   match(Set dst (ConvF2HF src));
> 11313:   format %{ "evcvtps2ph $dst,$src" %}

It will be good to also show the tmp register in the format.

src/hotspot/cpu/x86/x86_64.ad line 11323:

> 11321: 
> 11322: instruct convHF2F_reg_reg(regF dst, rRegI src) %{
> 11323:   predicate(VM_Version::supports_evex());

The predicate could be removed as it is fully covered in the match_rule_supported.

src/hotspot/share/opto/convertnode.cpp line 251:

> 249: //------------------------------Identity---------------------------------------
> 250: Node* ConvHF2FNode::Identity(PhaseGVN* phase) {
> 251:   return (in(1)->Opcode() == Op_ConvF2HF) ? in(1)->in(1) : this;

We cannot do this optimization:
     HF2F(F2HF(x)) != x 
This is because precision and range both are lost when we convert F2HF.

src/hotspot/share/opto/convertnode.hpp line 150:

> 148:   virtual const Type *bottom_type() const { return Type::FLOAT; }
> 149:   virtual const Type* Value(PhaseGVN* phase) const;
> 150:   virtual Node* Identity(PhaseGVN* phase);

The identity method could be removed from ConvHF2FNode

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PR: https://git.openjdk.org/jdk/pull/9781