RFR: 8341137: Optimize long vector multiplication using x86 VPMUL[U]DQ instruction

[Jasmine Karthikeyan]

On Sat, 19 Oct 2024 09:25:12 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> IMO until C2 type system starts to track bitwise constant information ([JDK-8001436](https://bugs.openjdk.org/browse/JDK-8001436) et al), there are not enough benefits to rely on IGVN here. So far, all the discussed patterns are simple enough for matcher to handle them without too much tweaking.
>
> Hi @iwanowww , 
> I have implemented additional pattern you suggested.
> In addition re-wiring pattern inputs to MulVL IR to avoid emitting upper doubleword clearing logic in applicable scenarios. 
> 
> Hi @jaskarth , @merykitty ,
> As discussed, waiting on PhaseLowering skeleton to move some part of this patch to x86 specific lowering pass.

Hi @jatin-bhateja, I've opened a PR for the new pass here: #21599. I've added just the skeleton code, like you suggested. Let me know what you think!

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PR Comment: https://git.openjdk.org/jdk/pull/21244#issuecomment-2425542577