RFR: 8342103: C2 compiler support for Float16 type and associated operations
Bhavana Kilambi
bkilambi at openjdk.org
Thu Nov 21 08:32:23 UTC 2024
On Thu, 21 Nov 2024 02:41:47 GMT, Hao Sun <haosun at openjdk.org> wrote:
>> Hi All,
>>
>> This patch adds C2 compiler support for various Float16 operations added by [PR#22128](https://github.com/openjdk/jdk/pull/22128)
>>
>> Following is the summary of changes included with this patch:-
>>
>> 1. Detection of various Float16 operations through inline expansion or pattern folding idealizations.
>> 2. Float16 operations like add, sub, mul, div, max, and min are inferred through pattern folding idealization.
>> 3. Float16 SQRT and FMA operation are inferred through inline expansion and their corresponding entry points are defined in the newly added Float16Math class.
>> - These intrinsics receive unwrapped short arguments encoding IEEE 754 binary16 values.
>> 5. New specialized IR nodes for Float16 operations, associated idealizations, and constant folding routines.
>> 6. New Ideal type for constant and non-constant Float16 IR nodes. Please refer to [FAQs ](https://github.com/openjdk/jdk/pull/21490#issuecomment-2482867818)for more details.
>> 7. Since Float16 uses short as its storage type, hence raw FP16 values are always loaded into general purpose register, but FP16 ISA instructions generally operate over floating point registers, therefore compiler injectes reinterpretation IR before and after Float16 operation nodes to move short value to floating point register and vice versa.
>> 8. New idealization routines to optimize redundant reinterpretation chains. HF2S + S2HF = HF
>> 6. Auto-vectorization of newly supported scalar operations.
>> 7. X86 and AARCH64 backend implementation for all supported intrinsics.
>> 9. Functional and Performance validation tests.
>>
>> **Missing Pieces:-**
>> **- AARCH64 Backend.**
>>
>> Kindly review and share your feedback.
>>
>> Best Regards,
>> Jatin
>
> Hi,
>
> Better to update the copyright year to 2024 for the following modified files:
>
>
> src/hotspot/share/adlc/output_h.cpp
> src/hotspot/share/opto/connode.cpp
> src/hotspot/share/opto/connode.hpp
> src/hotspot/share/opto/constantTable.cpp
> src/hotspot/share/opto/divnode.cpp
> src/hotspot/share/opto/divnode.hpp
> src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/amd64/AMD64.java
> test/hotspot/jtreg/compiler/lib/ir_framework/test/IREncodingPrinter.java
>
>
> I encountered one JTreg IR failure on AArch64 machine with SVE feature for `test/hotspot/jtreg/compiler/vectorization/TestFloat16VectorOperations.java` case. Here shows a snippet of the error log.
> If AArch64 backend part is not implemented, we'd better skip the IR verification on AArch64+SVE side.
>
>
> One or more @IR rules failed:
>
> Failed IR Rules (9) of Methods (9) ----------------------------------
> 1) Method "public void compiler.vectorization.TestFloat16VectorOperations.vectorAddFloat16()" - [Failed IR rules: 1]: * @IR rule 1: "@compiler.lib.ir_framework.IR(phase={DEFAULT}, applyIfPlatformAnd={}, applyIfCPUFeatureOr={"avx512_fp16", "true", "sve", "true"}, counts={"_#ADD_VHF#_", ">= 1"
> }, failOn={}, applyIfPlatform={}, applyIfPlatformOr={}, applyIfOr={}, applyIfCPUFeatureAnd={}, applyIf={}, applyIfCPUFeature={}, applyIfAnd={}, applyIfNot={})"
> > Phase "PrintIdeal":
> - counts: Graph contains wrong number of nodes:
> * Constraint 1: "(\d+(\s){2}(AddVHF.*)+(\s){2}===.*)" ...
Hi @shqking , thanks for your review. I am currently working on adding the aarch64 port for these operations. It's being done here - https://github.com/jatin-bhateja/jdk/pull/6. Do you think it's ok to keep the code as is for some more time until my patch is rebased and merged?
-------------
PR Comment: https://git.openjdk.org/jdk/pull/21490#issuecomment-2490369622
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