RFR: 8366444: Add support for add/mul reduction operations for Float16

[Xiaohong Gong]

On Thu, 2 Oct 2025 09:23:20 GMT, Bhavana Kilambi <bkilambi at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/aarch64_vector.ad line 272:
>> 
>>> 270:         if (length_in_bytes > 16 || !is_feat_fp16_supported()) {
>>> 271:           return false;
>>> 272:         }
>> 
>> Reductions with `length_in_bytes < 8` should also be skipped. Because such operations are not supported now, while the IRs with 32-bit vector size might exist, right?
>
> Hi @XiaohongGong, yes `length_in_bytes < 8` is also not supported and currently we support only for vector lengths of 8B and 16B.
> IRs with 32-bit vector size might exist but we do not have an optimized implementation for 32B vector lengths and thus I have disabled it. Instead of that, it generates the 16B scalarized Neon instruction sequence for a 32B vector length. Is this what you were asking?

I mean do we need to check the length_in_bytes < 8, such as:
Suggestion:

        if (length_in_bytes < 8 || length_in_bytes > 16 || !is_feat_fp16_supported()) {
          return false;
        }

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PR Review Comment: https://git.openjdk.org/jdk/pull/27526#discussion_r2409091499