Project proposal: RISC-V port
adinn at redhat.com
Fri Feb 9 14:08:05 UTC 2018
On 09/02/18 10:57, Edward Nevill wrote:
> I would like to voice my support for the creation of this project.
> I am happy to devote some 'spare' time to this project, but this will
> me limited to a few hours per week.
I wish I could make a similar offer but unfortunately I cannot make that
commitment at present.
> I agree with the overall approach you outline below. You will
> probably end up doing C1 anyway. The s390 port tried to do it without
> doing C1 and they ended up doing C1.
I'd second that view. Also, C1 is more valuable than it appears e.g. it
is still very valuable as a companion to Graal when the latter replaces
C2 via JVMCI.
> Andrew Haley's suggestion of using a built in simulator is a good
> one. This was the approach used on the aarch64 project and it was
> invaluable not just in terms of development time in the absence of
> hardware but in terms of debuggability. Also OpenJDK depends on a
> huge list of packages to build. Using this approach you can build and
> run on x86 while all the dependant packages are being ported.
I agree. This was an enormous boost to productivity when doing the
AArch64 port and I would recommend it to anyone doing a port --
especially while early chips still run the risk of hardware bugs.
Andrew Haley and I did document this process, albeit only in overview,
in our FOSDEM talk from 2013. I'd be happy to help anyone wishing to
attempt the same trick understand in more detail how we did it -- in
particular how we implemented debug support in the simulator (of course,
the AArch64 sim code, including debugger is still available on
sourceforge and the jdk code which used it is still in the AArch64 port
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