From scott at adligo.com Fri Oct 1 01:09:44 2021 From: scott at adligo.com (Scott Morgan) Date: Thu, 30 Sep 2021 20:09:44 -0500 Subject: Invocation API in JDK 9-17 Message-ID: Hi All, Does anyone know where the most recent documentation on the Invocation API is,? i.e. where is this for jdk 9-17, or was it removed or something? https://docs.oracle.com/javase/7/docs/technotes/guides/jni/spec/invocation.html https://docs.oracle.com/javase/8/docs/technotes/guides/jni/spec/invocation.html -- Regards, Scott Morgan President & CEO Adligo Inc http://www.adligo.com https://www.linkedin.com/in/scott-morgan-21739415 A+ Better Business Bureau Rating https://github.com/adligo By Appointment Only: 1-866-968-1893 Ex 101 scott at adligo.com skype:adligo1?call Send Me Files Securely: *https://www.sendthisfile.com/f.jsp?id=ewOnyeFQM18IDRf7MMIdolfI * https://discord.com/ Adligo#3066 From david.holmes at oracle.com Fri Oct 1 01:24:16 2021 From: david.holmes at oracle.com (David Holmes) Date: Fri, 1 Oct 2021 11:24:16 +1000 Subject: Invocation API in JDK 9-17 In-Reply-To: References: Message-ID: <1a867b45-0af6-de02-e31e-192cbc035653@oracle.com> Hi Scott, On 1/10/2021 11:09 am, Scott Morgan wrote: > Hi All, > > Does anyone know where the most recent documentation on the Invocation API > is,? > > i.e. where is this for jdk 9-17, or was it removed or something? > https://docs.oracle.com/javase/7/docs/technotes/guides/jni/spec/invocation.html > https://docs.oracle.com/javase/8/docs/technotes/guides/jni/spec/invocation.html Documentation was reorganised for 9+ and had another tweak for 11+ https://docs.oracle.com/javase/9/docs/specs/jni/ https://docs.oracle.com/javase/10/docs/specs/jni/ https://docs.oracle.com/en/java/javase/11/docs/specs/jni/ https://docs.oracle.com/en/java/javase/12/docs/specs/jni/ https://docs.oracle.com/en/java/javase/13/docs/specs/jni/ https://docs.oracle.com/en/java/javase/14/docs/specs/jni/ https://docs.oracle.com/en/java/javase/15/docs/specs/jni/ https://docs.oracle.com/en/java/javase/16/docs/specs/jni/ https://docs.oracle.com/en/java/javase/17/docs/specs/jni/ Please direct any discussion of JNI to hotspot-runtime-dev at openjdk.java.net Cheers, David > From sanhong.lsh at alibaba-inc.com Fri Oct 1 13:37:10 2021 From: sanhong.lsh at alibaba-inc.com (=?UTF-8?B?5p2O5LiJ57qiKOS4iee6oik=?=) Date: Fri, 01 Oct 2021 21:37:10 +0800 Subject: =?UTF-8?B?562U5aSNOiBDYWxsIGZvciBEaXNjdXNzaW9uOiBOZXcgUHJvamVjdDogUklTQy1WIFBvcnQ=?= In-Reply-To: References: Message-ID: <002901d7b6c9$6fd8a630$4f89f290$@alibaba-inc.com> Hi, Thanks for raising this discussion. We (Alibaba) would like to voice the support for creating this project and contribute our efforts to this project. RISC-V?as an open standard ISA has been supported in other popular runtime/compilers, likes V8, Go, LLVM, etc. It's time to consider moving forward with Java, and we believe this porting work will benefit the broader Java ecosystem. Alibaba already co-worked with Huawei and participated in the OpenJDK RV64 Porting Work [1] under RVI [2]. Most development work has also been synced up with the JDK sandbox [3]. We are examining the next step to discuss the possible practicalities of getting these changes into the mainline. Because the proposing project sounds to go under Porters Group, so maybe - @Dalibor, can Porters Group sponsor this project? Thanks Sanhong [1] https://github.com/riscv-collab/riscv-openjdk [2] https://riscv.org/ [3] https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch -----????----- ???: discuss ?? Yangfei (Felix) ????: 2021?9?29? 9:42 ???: Andrew Dinn ; discuss at openjdk.java.net ??: RE: Call for Discussion: New Project: RISC-V Port Hi Andrew, > -----Original Message----- > From: Andrew Dinn [mailto:adinn at redhat.com] > Sent: Tuesday, September 28, 2021 8:50 PM > To: Yangfei (Felix) ; discuss at openjdk.java.net > Subject: Re: Call for Discussion: New Project: RISC-V Port > > On 27/09/2021 12:09, Yangfei (Felix) wrote: > > We would like to propose a new project called "RISC-V Port". > I am not in a position to speak on behalf of Red Hat. However, > speaking personally I support adding this porting project. I will not > be able to contribute a lot of time to it but I will do my best to > offer help and/or advice where I can. Thanks for your support. I want to emphasize that the experience of how the AArch64 port was done is immensely valuable for us working on this RISC-V port. I believe development and upstreaming of the AArch64 port will pave the way for this new proposed project. Thanks, Felix. From dalibor.topic at oracle.com Fri Oct 1 20:24:28 2021 From: dalibor.topic at oracle.com (Dalibor Topic) Date: Fri, 1 Oct 2021 22:24:28 +0200 Subject: =?UTF-8?B?UmU6IOetlOWkjTogQ2FsbCBmb3IgRGlzY3Vzc2lvbjogTmV3IFByb2pl?= =?UTF-8?Q?ct=3a_RISC-V_Port?= In-Reply-To: <002901d7b6c9$6fd8a630$4f89f290$@alibaba-inc.com> References: <002901d7b6c9$6fd8a630$4f89f290$@alibaba-inc.com> Message-ID: <0a919e0f-8757-3fd2-d54f-d8493dc75bbb@oracle.com> On 01.10.2021 15:37, ???(??) wrote: > Hi, > Thanks for raising this discussion. We (Alibaba) would like to voice the support for creating this project and contribute our efforts to this project. > > RISC-V?as an open standard ISA has been supported in other popular runtime/compilers, likes V8, Go, LLVM, etc. It's time to consider moving forward with Java, and we believe this porting work will benefit the broader Java ecosystem. > > Alibaba already co-worked with Huawei and participated in the OpenJDK RV64 Porting Work [1] under RVI [2]. Most development work has also been synced up with the JDK sandbox [3]. We are examining the next step to discuss the possible practicalities of getting these changes into the mainline. > > Because the proposing project sounds to go under Porters Group, so maybe - > @Dalibor, can Porters Group sponsor this project? Hi Sanhong, hi Felix - I agree that the Porters Group should sponsor this new project. cheers, dalibor topic > > Thanks > Sanhong > > [1] https://github.com/riscv-collab/riscv-openjdk > [2] https://riscv.org/ > [3] https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > -----????----- > ???: discuss ?? Yangfei (Felix) > ????: 2021?9?29? 9:42 > ???: Andrew Dinn ; discuss at openjdk.java.net > ??: RE: Call for Discussion: New Project: RISC-V Port > > Hi Andrew, > >> -----Original Message----- >> From: Andrew Dinn [mailto:adinn at redhat.com] >> Sent: Tuesday, September 28, 2021 8:50 PM >> To: Yangfei (Felix) ; discuss at openjdk.java.net >> Subject: Re: Call for Discussion: New Project: RISC-V Port >> >> On 27/09/2021 12:09, Yangfei (Felix) wrote: >>> We would like to propose a new project called "RISC-V Port". >> I am not in a position to speak on behalf of Red Hat. However, >> speaking personally I support adding this porting project. I will not >> be able to contribute a lot of time to it but I will do my best to >> offer help and/or advice where I can. > > Thanks for your support. > I want to emphasize that the experience of how the AArch64 port was done is immensely valuable for us working on this RISC-V port. > I believe development and upstreaming of the AArch64 port will pave the way for this new proposed project. > > Thanks, > Felix. > -- Dalibor Topic Consulting Product Manager Phone: +494089091214 , Mobile: +491737185961 , Video: dalibor.topic at oracle.com Oracle Global Services Germany GmbH Hauptverwaltung: Riesstr. 25, D-80992 M?nchen Registergericht: Amtsgericht M?nchen, HRB 246209 Gesch?ftsf?hrer: Ralf Herrmann From felix.yang at huawei.com Sat Oct 2 12:15:48 2021 From: felix.yang at huawei.com (Yangfei (Felix)) Date: Sat, 2 Oct 2021 12:15:48 +0000 Subject: =?utf-8?B?UkU6IOetlOWkjTogQ2FsbCBmb3IgRGlzY3Vzc2lvbjogTmV3IFByb2plY3Q6?= =?utf-8?Q?_RISC-V_Port?= In-Reply-To: <0a919e0f-8757-3fd2-d54f-d8493dc75bbb@oracle.com> References: <002901d7b6c9$6fd8a630$4f89f290$@alibaba-inc.com> <0a919e0f-8757-3fd2-d54f-d8493dc75bbb@oracle.com> Message-ID: Hi Dalibor, > -----Original Message----- > From: discuss [mailto:discuss-retn at openjdk.java.net] On Behalf Of Dalibor > Topic > Sent: Saturday, October 2, 2021 4:24 AM > To: discuss at openjdk.java.net > Subject: Re: ??: Call for Discussion: New Project: RISC-V Port > > > > On 01.10.2021 15:37, ???(??) wrote: > > Hi, > > Thanks for raising this discussion. We (Alibaba) would like to voice the > support for creating this project and contribute our efforts to this project. > > > > RISC-V?as an open standard ISA has been supported in other popular > runtime/compilers, likes V8, Go, LLVM, etc. It's time to consider moving > forward with Java, and we believe this porting work will benefit the broader > Java ecosystem. > > > > Alibaba already co-worked with Huawei and participated in the OpenJDK > RV64 Porting Work [1] under RVI [2]. Most development work has also been > synced up with the JDK sandbox [3]. We are examining the next step to > discuss the possible practicalities of getting these changes into the mainline. > > > > Because the proposing project sounds to go under Porters Group, so > > maybe - @Dalibor, can Porters Group sponsor this project? > > Hi Sanhong, hi Felix - I agree that the Porters Group should sponsor this new > project. > > cheers, > dalibor topic I am very glad to hear that : - ) Thanks for the support. Cheers, Felix From aph-open at littlepinkcloud.com Sat Oct 2 16:01:16 2021 From: aph-open at littlepinkcloud.com (Andrew Haley) Date: Sat, 2 Oct 2021 17:01:16 +0100 Subject: Call for Discussion: New Project: RISC-V Port In-Reply-To: References: Message-ID: On 9/27/21 12:09 PM, Yangfei (Felix) wrote: > We would like to propose a new project called "RISC-V Port". Good idea! It's time to bring RISC-V into the OpenJDK family. -- Andrew Haley (he/him) Java Platform Lead Engineer Red Hat UK Ltd. https://keybase.io/andrewhaley EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671 From sanhong.lsh at alibaba-inc.com Sun Oct 3 16:17:33 2021 From: sanhong.lsh at alibaba-inc.com (=?UTF-8?B?5p2O5LiJ57qiKOS4iee6oik=?=) Date: Mon, 04 Oct 2021 00:17:33 +0800 Subject: =?UTF-8?B?562U5aSNOiDnrZTlpI06IENhbGwgZm9yIERpc2N1c3Npb246IE5ldyBQcm9qZWN0OiBSSVND?= =?UTF-8?B?LVYgUG9ydA==?= In-Reply-To: <0a919e0f-8757-3fd2-d54f-d8493dc75bbb@oracle.com> References: <002901d7b6c9$6fd8a630$4f89f290$@alibaba-inc.com> <0a919e0f-8757-3fd2-d54f-d8493dc75bbb@oracle.com> Message-ID: <005201d7b872$2c1b7b20$84527160$@alibaba-inc.com> HI Dalibor, Thank you for offering to sponsor this project! Let's continue on the path of taking RISC-V into the mainline:) Thanks! Sanhong -----????----- ???: discuss ?? Dalibor Topic ????: 2021?10?2? 4:24 ???: discuss at openjdk.java.net ??: Re: ??: Call for Discussion: New Project: RISC-V Port On 01.10.2021 15:37, ???(??) wrote: > Hi, > Thanks for raising this discussion. We (Alibaba) would like to voice the support for creating this project and contribute our efforts to this project. > > RISC-V?as an open standard ISA has been supported in other popular runtime/compilers, likes V8, Go, LLVM, etc. It's time to consider moving forward with Java, and we believe this porting work will benefit the broader Java ecosystem. > > Alibaba already co-worked with Huawei and participated in the OpenJDK RV64 Porting Work [1] under RVI [2]. Most development work has also been synced up with the JDK sandbox [3]. We are examining the next step to discuss the possible practicalities of getting these changes into the mainline. > > Because the proposing project sounds to go under Porters Group, so > maybe - @Dalibor, can Porters Group sponsor this project? Hi Sanhong, hi Felix - I agree that the Porters Group should sponsor this new project. cheers, dalibor topic > > Thanks > Sanhong > > [1] https://github.com/riscv-collab/riscv-openjdk > [2] https://riscv.org/ > [3] https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > -----????----- > ???: discuss ?? Yangfei (Felix) > ????: 2021?9?29? 9:42 > ???: Andrew Dinn ; discuss at openjdk.java.net > ??: RE: Call for Discussion: New Project: RISC-V Port > > Hi Andrew, > >> -----Original Message----- >> From: Andrew Dinn [mailto:adinn at redhat.com] >> Sent: Tuesday, September 28, 2021 8:50 PM >> To: Yangfei (Felix) ; discuss at openjdk.java.net >> Subject: Re: Call for Discussion: New Project: RISC-V Port >> >> On 27/09/2021 12:09, Yangfei (Felix) wrote: >>> We would like to propose a new project called "RISC-V Port". >> I am not in a position to speak on behalf of Red Hat. However, >> speaking personally I support adding this porting project. I will not >> be able to contribute a lot of time to it but I will do my best to >> offer help and/or advice where I can. > > Thanks for your support. > I want to emphasize that the experience of how the AArch64 port was done is immensely valuable for us working on this RISC-V port. > I believe development and upstreaming of the AArch64 port will pave the way for this new proposed project. > > Thanks, > Felix. > -- Dalibor Topic Consulting Product Manager Phone: +494089091214 , Mobile: +491737185961 , Video: dalibor.topic at oracle.com Oracle Global Services Germany GmbH Hauptverwaltung: Riesstr. 25, D-80992 M?nchen Registergericht: Amtsgericht M?nchen, HRB 246209 Gesch?ftsf?hrer: Ralf Herrmann From shade at redhat.com Tue Oct 12 05:50:09 2021 From: shade at redhat.com (Aleksey Shipilev) Date: Tue, 12 Oct 2021 07:50:09 +0200 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: <5a5906db-f27a-a835-c98f-b7b8f890218a@redhat.com> Vote: yes On 10/11/21 4:39 AM, Yangfei (Felix) wrote: > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. -- Thanks, -Aleksey From sgehwolf at redhat.com Tue Oct 12 09:20:14 2021 From: sgehwolf at redhat.com (Severin Gehwolf) Date: Tue, 12 Oct 2021 11:20:14 +0200 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: <903140e1ab37734ce8f4f9ac091eea0818945bf4.camel@redhat.com> Vote: yes On Mon, 2021-10-11 at 02:39 +0000, Yangfei (Felix) wrote: > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. From volker.simonis at gmail.com Tue Oct 12 09:21:04 2021 From: volker.simonis at gmail.com (Volker Simonis) Date: Tue, 12 Oct 2021 10:21:04 +0100 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: Vote: yes Yangfei (Felix) schrieb am Mo., 11. Okt. 2021, 19:27: > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. > > The goal of the project will be to provide a full featured port of OpenJDK > on the RISC-V platform. The current project would only target Linux. > RISC-V > ISA is actually a family of related ISAs of which there are currently four > base ISAs [2]. Those base ISAs can be combined with a set of standard > extensions. RV64G and RV32G are defined as general-purpose ISAs. This port > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for > vector operations [3]. And the implementation will be fully compatible > with > RISC-V ISA specifications. This port may support other ISA variants like > RV32G depending on community interest. > > We (Huawei Technologies) already have a complete (i.e. template > interpreter, > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent > snapshot > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should > be > good enough to run most Java programs. The VectorAPI and ForeignAPI > features > are not supported for now. Support for vector operations is experimental, > we > need to do more testing for this part. We've provided full build > instructions > [4], but we'll help you if you get stuck. Aleksey Shipilev is building > riscv-port-branch nightlies here [5]. We want people to try it out. > > We intend to continuously rebase the source code to the latest JDK > mainline, and > then, after a round of in-project reviews, suggest it for integration into > JDK > mainline. If this project is approved, I believe we still have time to > submit > the integration JEP targeting JDK 18. We would welcome your advice and > guidance about this. > > We will consider 17u and 11u backports, after JDK mainline integration is > done. > This, of course, depends on whether the 17u and 11u maintainers would > approve > such backport. > > Fei Yang has been working on OpenJDK for aarch64 port project since year > 2015 > and is an OpenJDK committer [6]. He is currently a major developer for > OpenJDK > RISC-V port and has reviewed most of the code changes internally. > Previously, > he is also a GCC committer [7] and has contributed various performance and > bugfixes since year 2013. > > The proposed initial set of reviewers are: > > Fei Yang > Aleksey Shipilev > Edward Nevill > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > Only current OpenJDK Members [8] are eligible to vote on this > motion. Votes must be cast in the open on the discuss list. > Replying to this message is sufficient if your mail program > honors the Reply-To header. > > For Lazy Consensus voting instructions, see [9]. > > Fei Yang > > [1] > https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html > [2] https://github.com/riscv/riscv-isa-manual > [3] > https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf > [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > [5] https://builds.shipilev.net/openjdk-jdk-riscv > [6] http://openjdk.java.net/census#fyang > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > [8] http://openjdk.java.net/census#members > [9] http://openjdk.java.net/projects/#new-project-vote > From adinn at redhat.com Tue Oct 12 09:36:11 2021 From: adinn at redhat.com (Andrew Dinn) Date: Tue, 12 Oct 2021 10:36:11 +0100 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: <7194bd5a-098d-7665-691c-42c321ee32fa@redhat.com> Vote: yes On 11/10/2021 03:39, Yangfei (Felix) wrote: > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. > > The goal of the project will be to provide a full featured port of OpenJDK > on the RISC-V platform. The current project would only target Linux. RISC-V > ISA is actually a family of related ISAs of which there are currently four > base ISAs [2]. Those base ISAs can be combined with a set of standard > extensions. RV64G and RV32G are defined as general-purpose ISAs. This port > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for > vector operations [3]. And the implementation will be fully compatible with > RISC-V ISA specifications. This port may support other ISA variants like > RV32G depending on community interest. > > We (Huawei Technologies) already have a complete (i.e. template interpreter, > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent snapshot > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should be > good enough to run most Java programs. The VectorAPI and ForeignAPI features > are not supported for now. Support for vector operations is experimental, we > need to do more testing for this part. We've provided full build instructions > [4], but we'll help you if you get stuck. Aleksey Shipilev is building > riscv-port-branch nightlies here [5]. We want people to try it out. > > We intend to continuously rebase the source code to the latest JDK mainline, and > then, after a round of in-project reviews, suggest it for integration into JDK > mainline. If this project is approved, I believe we still have time to submit > the integration JEP targeting JDK 18. We would welcome your advice and > guidance about this. > > We will consider 17u and 11u backports, after JDK mainline integration is done. > This, of course, depends on whether the 17u and 11u maintainers would approve > such backport. > > Fei Yang has been working on OpenJDK for aarch64 port project since year 2015 > and is an OpenJDK committer [6]. He is currently a major developer for OpenJDK > RISC-V port and has reviewed most of the code changes internally. Previously, > he is also a GCC committer [7] and has contributed various performance and > bugfixes since year 2013. > > The proposed initial set of reviewers are: > > Fei Yang > Aleksey Shipilev > Edward Nevill > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > Only current OpenJDK Members [8] are eligible to vote on this > motion. Votes must be cast in the open on the discuss list. > Replying to this message is sufficient if your mail program > honors the Reply-To header. > > For Lazy Consensus voting instructions, see [9]. > > Fei Yang > > [1] https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html > [2] https://github.com/riscv/riscv-isa-manual > [3] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf > [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > [5] https://builds.shipilev.net/openjdk-jdk-riscv > [6] http://openjdk.java.net/census#fyang > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > [8] http://openjdk.java.net/census#members > [9] http://openjdk.java.net/projects/#new-project-vote > -- regards, Andrew Dinn ----------- Red Hat Distinguished Engineer Red Hat UK Ltd Registered in England and Wales under Company Registration No. 03798903 Directors: Michael Cunningham, Michael ("Mike") O'Neill From thomas.stuefe at gmail.com Tue Oct 12 09:41:09 2021 From: thomas.stuefe at gmail.com (=?UTF-8?Q?Thomas_St=C3=BCfe?=) Date: Tue, 12 Oct 2021 11:41:09 +0200 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: Vote: yes On Mon, Oct 11, 2021 at 8:27 PM Yangfei (Felix) wrote: > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. > > The goal of the project will be to provide a full featured port of OpenJDK > on the RISC-V platform. The current project would only target Linux. > RISC-V > ISA is actually a family of related ISAs of which there are currently four > base ISAs [2]. Those base ISAs can be combined with a set of standard > extensions. RV64G and RV32G are defined as general-purpose ISAs. This port > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for > vector operations [3]. And the implementation will be fully compatible > with > RISC-V ISA specifications. This port may support other ISA variants like > RV32G depending on community interest. > > We (Huawei Technologies) already have a complete (i.e. template > interpreter, > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent > snapshot > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should > be > good enough to run most Java programs. The VectorAPI and ForeignAPI > features > are not supported for now. Support for vector operations is experimental, > we > need to do more testing for this part. We've provided full build > instructions > [4], but we'll help you if you get stuck. Aleksey Shipilev is building > riscv-port-branch nightlies here [5]. We want people to try it out. > > We intend to continuously rebase the source code to the latest JDK > mainline, and > then, after a round of in-project reviews, suggest it for integration into > JDK > mainline. If this project is approved, I believe we still have time to > submit > the integration JEP targeting JDK 18. We would welcome your advice and > guidance about this. > > We will consider 17u and 11u backports, after JDK mainline integration is > done. > This, of course, depends on whether the 17u and 11u maintainers would > approve > such backport. > > Fei Yang has been working on OpenJDK for aarch64 port project since year > 2015 > and is an OpenJDK committer [6]. He is currently a major developer for > OpenJDK > RISC-V port and has reviewed most of the code changes internally. > Previously, > he is also a GCC committer [7] and has contributed various performance and > bugfixes since year 2013. > > The proposed initial set of reviewers are: > > Fei Yang > Aleksey Shipilev > Edward Nevill > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > Only current OpenJDK Members [8] are eligible to vote on this > motion. Votes must be cast in the open on the discuss list. > Replying to this message is sufficient if your mail program > honors the Reply-To header. > > For Lazy Consensus voting instructions, see [9]. > > Fei Yang > > [1] > https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html > [2] https://github.com/riscv/riscv-isa-manual > [3] > https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf > [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > [5] https://builds.shipilev.net/openjdk-jdk-riscv > [6] http://openjdk.java.net/census#fyang > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > [8] http://openjdk.java.net/census#members > [9] http://openjdk.java.net/projects/#new-project-vote > From zgu at redhat.com Tue Oct 12 11:50:42 2021 From: zgu at redhat.com (Zhengyu Gu) Date: Tue, 12 Oct 2021 07:50:42 -0400 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: <21441b5d-b3e6-4747-0753-1d0d7751e6ac@redhat.com> Vote: yes -Zhengyu On 10/10/21 22:39, Yangfei (Felix) wrote: > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. > > The goal of the project will be to provide a full featured port of OpenJDK > on the RISC-V platform. The current project would only target Linux. RISC-V > ISA is actually a family of related ISAs of which there are currently four > base ISAs [2]. Those base ISAs can be combined with a set of standard > extensions. RV64G and RV32G are defined as general-purpose ISAs. This port > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for > vector operations [3]. And the implementation will be fully compatible with > RISC-V ISA specifications. This port may support other ISA variants like > RV32G depending on community interest. > > We (Huawei Technologies) already have a complete (i.e. template interpreter, > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent snapshot > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should be > good enough to run most Java programs. The VectorAPI and ForeignAPI features > are not supported for now. Support for vector operations is experimental, we > need to do more testing for this part. We've provided full build instructions > [4], but we'll help you if you get stuck. Aleksey Shipilev is building > riscv-port-branch nightlies here [5]. We want people to try it out. > > We intend to continuously rebase the source code to the latest JDK mainline, and > then, after a round of in-project reviews, suggest it for integration into JDK > mainline. If this project is approved, I believe we still have time to submit > the integration JEP targeting JDK 18. We would welcome your advice and > guidance about this. > > We will consider 17u and 11u backports, after JDK mainline integration is done. > This, of course, depends on whether the 17u and 11u maintainers would approve > such backport. > > Fei Yang has been working on OpenJDK for aarch64 port project since year 2015 > and is an OpenJDK committer [6]. He is currently a major developer for OpenJDK > RISC-V port and has reviewed most of the code changes internally. Previously, > he is also a GCC committer [7] and has contributed various performance and > bugfixes since year 2013. > > The proposed initial set of reviewers are: > > Fei Yang > Aleksey Shipilev > Edward Nevill > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > Only current OpenJDK Members [8] are eligible to vote on this > motion. Votes must be cast in the open on the discuss list. > Replying to this message is sufficient if your mail program > honors the Reply-To header. > > For Lazy Consensus voting instructions, see [9]. > > Fei Yang > > [1] https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html > [2] https://github.com/riscv/riscv-isa-manual > [3] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf > [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > [5] https://builds.shipilev.net/openjdk-jdk-riscv > [6] http://openjdk.java.net/census#fyang > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > [8] http://openjdk.java.net/census#members > [9] http://openjdk.java.net/projects/#new-project-vote > From edward.nevill at gmail.com Tue Oct 12 13:22:39 2021 From: edward.nevill at gmail.com (Edward Nevill) Date: Tue, 12 Oct 2021 14:22:39 +0100 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: <8ba923ef293da148011bd19281c82b84f51a7ade.camel@gmail.com> I am fully in support of this port and think it is high time RISC-V was added to the supported architectures. Sadly I am unable to vote as I am not a member of the OpenJDK members group. All the best, Ed. On Mon, 2021-10-11 at 02:39 +0000, Yangfei (Felix) wrote: > I hereby propose the creation of the "RISC-V Port" Project with Fei > Yang > as the Lead and Porters Group as the sponsoring group [1]. > > The goal of the project will be to provide a full featured port of > OpenJDK > on the RISC-V platform. The current project would only target Linux. > RISC-V > ISA is actually a family of related ISAs of which there are currently > four > base ISAs [2]. Those base ISAs can be combined with a set of > standard > extensions. RV64G and RV32G are defined as general-purpose > ISAs. This port > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension > for > vector operations [3]. And the implementation will be fully > compatible with > RISC-V ISA specifications. This port may support other ISA variants > like > RV32G depending on community interest. > > We (Huawei Technologies) already have a complete (i.e. template > interpreter, > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent > snapshot > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it > should be > good enough to run most Java programs. The VectorAPI and ForeignAPI > features > are not supported for now. Support for vector operations is > experimental, we > need to do more testing for this part. We've provided full build > instructions > [4], but we'll help you if you get stuck. Aleksey Shipilev is > building > riscv-port-branch nightlies here [5]. We want people to try it out. > > We intend to continuously rebase the source code to the latest JDK > mainline, and > then, after a round of in-project reviews, suggest it for integration > into JDK > mainline. If this project is approved, I believe we still have time > to submit > the integration JEP targeting JDK 18. We would welcome your advice > and > guidance about this. > > We will consider 17u and 11u backports, after JDK mainline > integration is done. > This, of course, depends on whether the 17u and 11u maintainers would > approve > such backport. > > Fei Yang has been working on OpenJDK for aarch64 port project since > year 2015 > and is an OpenJDK committer [6]. He is currently a major developer > for OpenJDK > RISC-V port and has reviewed most of the code changes > internally. Previously, > he is also a GCC committer [7] and has contributed various > performance and > bugfixes since year 2013. > > The proposed initial set of reviewers are: > > Fei Yang > Aleksey Shipilev > Edward Nevill > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > Only current OpenJDK Members [8] are eligible to vote on this > motion. Votes must be cast in the open on the discuss list. > Replying to this message is sufficient if your mail program > honors the Reply-To header. > > For Lazy Consensus voting instructions, see [9]. > > Fei Yang > > [1] > https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html > [2] https://github.com/riscv/riscv-isa-manual > [3] > https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf > [4] > http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > [5] https://builds.shipilev.net/openjdk-jdk-riscv > [6] http://openjdk.java.net/census#fyang > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > [8] http://openjdk.java.net/census#members > [9] http://openjdk.java.net/projects/#new-project-vote From dalibor.topic at oracle.com Tue Oct 12 15:36:01 2021 From: dalibor.topic at oracle.com (Dalibor Topic) Date: Tue, 12 Oct 2021 17:36:01 +0200 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: Vote: Yes. On 11.10.2021 04:39, Yangfei (Felix) wrote: > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1] -- Dalibor Topic Consulting Product Manager Phone: +494089091214 , Mobile: +491737185961 , Video: dalibor.topic at oracle.com Oracle Global Services Germany GmbH Hauptverwaltung: Riesstr. 25, D-80992 M?nchen Registergericht: Amtsgericht M?nchen, HRB 246209 Gesch?ftsf?hrer: Ralf Herrmann From vladimir.kozlov at oracle.com Tue Oct 12 16:10:19 2021 From: vladimir.kozlov at oracle.com (Vladimir Kozlov) Date: Tue, 12 Oct 2021 09:10:19 -0700 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: <12d5155a-f987-6806-0fcd-25986a2cffb6@oracle.com> Vote: yes Thanks, Vladimir K On 10/10/21 7:39 PM, Yangfei (Felix) wrote: > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. > > The goal of the project will be to provide a full featured port of OpenJDK > on the RISC-V platform. The current project would only target Linux. RISC-V > ISA is actually a family of related ISAs of which there are currently four > base ISAs [2]. Those base ISAs can be combined with a set of standard > extensions. RV64G and RV32G are defined as general-purpose ISAs. This port > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for > vector operations [3]. And the implementation will be fully compatible with > RISC-V ISA specifications. This port may support other ISA variants like > RV32G depending on community interest. > > We (Huawei Technologies) already have a complete (i.e. template interpreter, > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent snapshot > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should be > good enough to run most Java programs. The VectorAPI and ForeignAPI features > are not supported for now. Support for vector operations is experimental, we > need to do more testing for this part. We've provided full build instructions > [4], but we'll help you if you get stuck. Aleksey Shipilev is building > riscv-port-branch nightlies here [5]. We want people to try it out. > > We intend to continuously rebase the source code to the latest JDK mainline, and > then, after a round of in-project reviews, suggest it for integration into JDK > mainline. If this project is approved, I believe we still have time to submit > the integration JEP targeting JDK 18. We would welcome your advice and > guidance about this. > > We will consider 17u and 11u backports, after JDK mainline integration is done. > This, of course, depends on whether the 17u and 11u maintainers would approve > such backport. > > Fei Yang has been working on OpenJDK for aarch64 port project since year 2015 > and is an OpenJDK committer [6]. He is currently a major developer for OpenJDK > RISC-V port and has reviewed most of the code changes internally. Previously, > he is also a GCC committer [7] and has contributed various performance and > bugfixes since year 2013. > > The proposed initial set of reviewers are: > > Fei Yang > Aleksey Shipilev > Edward Nevill > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > Only current OpenJDK Members [8] are eligible to vote on this > motion. Votes must be cast in the open on the discuss list. > Replying to this message is sufficient if your mail program > honors the Reply-To header. > > For Lazy Consensus voting instructions, see [9]. > > Fei Yang > > [1] https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html > [2] https://github.com/riscv/riscv-isa-manual > [3] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf > [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > [5] https://builds.shipilev.net/openjdk-jdk-riscv > [6] http://openjdk.java.net/census#fyang > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > [8] http://openjdk.java.net/census#members > [9] http://openjdk.java.net/projects/#new-project-vote > From hohensee at amazon.com Tue Oct 12 17:03:57 2021 From: hohensee at amazon.com (Hohensee, Paul) Date: Tue, 12 Oct 2021 17:03:57 +0000 Subject: CFV: New Project: RISC-V Port Message-ID: <2781927C-F1D2-46FC-A7E1-4EC2F9E9697F@amazon.com> Vote: yes ?-----Original Message----- From: announce on behalf of "Yangfei (Felix)" Reply-To: "discuss at openjdk.java.net" Date: Monday, October 11, 2021 at 11:28 AM To: "announce at openjdk.java.net" Subject: CFV: New Project: RISC-V Port I hereby propose the creation of the "RISC-V Port" Project with Fei Yang as the Lead and Porters Group as the sponsoring group [1]. The goal of the project will be to provide a full featured port of OpenJDK on the RISC-V platform. The current project would only target Linux. RISC-V ISA is actually a family of related ISAs of which there are currently four base ISAs [2]. Those base ISAs can be combined with a set of standard extensions. RV64G and RV32G are defined as general-purpose ISAs. This port will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for vector operations [3]. And the implementation will be fully compatible with RISC-V ISA specifications. This port may support other ISA variants like RV32G depending on community interest. We (Huawei Technologies) already have a complete (i.e. template interpreter, C1 and C2 JIT) RISC-V port. This work is based on reasonably recent snapshot of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should be good enough to run most Java programs. The VectorAPI and ForeignAPI features are not supported for now. Support for vector operations is experimental, we need to do more testing for this part. We've provided full build instructions [4], but we'll help you if you get stuck. Aleksey Shipilev is building riscv-port-branch nightlies here [5]. We want people to try it out. We intend to continuously rebase the source code to the latest JDK mainline, and then, after a round of in-project reviews, suggest it for integration into JDK mainline. If this project is approved, I believe we still have time to submit the integration JEP targeting JDK 18. We would welcome your advice and guidance about this. We will consider 17u and 11u backports, after JDK mainline integration is done. This, of course, depends on whether the 17u and 11u maintainers would approve such backport. Fei Yang has been working on OpenJDK for aarch64 port project since year 2015 and is an OpenJDK committer [6]. He is currently a major developer for OpenJDK RISC-V port and has reviewed most of the code changes internally. Previously, he is also a GCC committer [7] and has contributed various performance and bugfixes since year 2013. The proposed initial set of reviewers are: Fei Yang Aleksey Shipilev Edward Nevill Votes are due by 9:00 UTC on Monday 25, October 2021 Only current OpenJDK Members [8] are eligible to vote on this motion. Votes must be cast in the open on the discuss list. Replying to this message is sufficient if your mail program honors the Reply-To header. For Lazy Consensus voting instructions, see [9]. Fei Yang [1] https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html [2] https://github.com/riscv/riscv-isa-manual [3] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md [5] https://builds.shipilev.net/openjdk-jdk-riscv [6] http://openjdk.java.net/census#fyang [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS [8] http://openjdk.java.net/census#members [9] http://openjdk.java.net/projects/#new-project-vote From serguei.spitsyn at oracle.com Tue Oct 12 17:29:27 2021 From: serguei.spitsyn at oracle.com (Serguei Spitsyn) Date: Tue, 12 Oct 2021 17:29:27 +0000 Subject: New Project: RISC-V Port Message-ID: Vote: yes ?On 10/11/21, 11:27 AM, "announce on behalf of Yangfei (Felix)" wrote: I hereby propose the creation of the "RISC-V Port" Project with Fei Yang as the Lead and Porters Group as the sponsoring group [1]. From joe.darcy at oracle.com Tue Oct 12 18:03:27 2021 From: joe.darcy at oracle.com (Joe Darcy) Date: Tue, 12 Oct 2021 11:03:27 -0700 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: <2fe176e3-f816-6955-0e45-2276cde27306@oracle.com> Vote: yes -Joe On 10/10/2021 7:39 PM, Yangfei (Felix) wrote: > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. > > The goal of the project will be to provide a full featured port of OpenJDK > on the RISC-V platform. The current project would only target Linux. RISC-V > ISA is actually a family of related ISAs of which there are currently four > base ISAs [2]. Those base ISAs can be combined with a set of standard > extensions. RV64G and RV32G are defined as general-purpose ISAs. This port > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for > vector operations [3]. And the implementation will be fully compatible with > RISC-V ISA specifications. This port may support other ISA variants like > RV32G depending on community interest. > > We (Huawei Technologies) already have a complete (i.e. template interpreter, > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent snapshot > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should be > good enough to run most Java programs. The VectorAPI and ForeignAPI features > are not supported for now. Support for vector operations is experimental, we > need to do more testing for this part. We've provided full build instructions > [4], but we'll help you if you get stuck. Aleksey Shipilev is building > riscv-port-branch nightlies here [5]. We want people to try it out. > > We intend to continuously rebase the source code to the latest JDK mainline, and > then, after a round of in-project reviews, suggest it for integration into JDK > mainline. If this project is approved, I believe we still have time to submit > the integration JEP targeting JDK 18. We would welcome your advice and > guidance about this. > > We will consider 17u and 11u backports, after JDK mainline integration is done. > This, of course, depends on whether the 17u and 11u maintainers would approve > such backport. > > Fei Yang has been working on OpenJDK for aarch64 port project since year 2015 > and is an OpenJDK committer [6]. He is currently a major developer for OpenJDK > RISC-V port and has reviewed most of the code changes internally. Previously, > he is also a GCC committer [7] and has contributed various performance and > bugfixes since year 2013. > > The proposed initial set of reviewers are: > > Fei Yang > Aleksey Shipilev > Edward Nevill > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > Only current OpenJDK Members [8] are eligible to vote on this > motion. Votes must be cast in the open on the discuss list. > Replying to this message is sufficient if your mail program > honors the Reply-To header. > > For Lazy Consensus voting instructions, see [9]. > > Fei Yang > > [1] https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html > [2] https://github.com/riscv/riscv-isa-manual > [3] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf > [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > [5] https://builds.shipilev.net/openjdk-jdk-riscv > [6] http://openjdk.java.net/census#fyang > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > [8] http://openjdk.java.net/census#members > [9] http://openjdk.java.net/projects/#new-project-vote From paul.sandoz at oracle.com Tue Oct 12 19:44:40 2021 From: paul.sandoz at oracle.com (Paul Sandoz) Date: Tue, 12 Oct 2021 19:44:40 +0000 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: <66637BDB-8DA6-4395-B3D3-5BE031302EA5@oracle.com> Vote: yes. ? A word of caution: I think it a little premature to consider a target release at this point. In my experience it is very easy underestimate the time required to properly shepherd a JEP of this potential magnitude through the OpenJDK review process. I can understand the desire but I see no reason to rush given the 6 month release cadence. Paul. > On Oct 10, 2021, at 7:39 PM, Yangfei (Felix) wrote: > > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. > > The goal of the project will be to provide a full featured port of OpenJDK > on the RISC-V platform. The current project would only target Linux. RISC-V > ISA is actually a family of related ISAs of which there are currently four > base ISAs [2]. Those base ISAs can be combined with a set of standard > extensions. RV64G and RV32G are defined as general-purpose ISAs. This port > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for > vector operations [3]. And the implementation will be fully compatible with > RISC-V ISA specifications. This port may support other ISA variants like > RV32G depending on community interest. > > We (Huawei Technologies) already have a complete (i.e. template interpreter, > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent snapshot > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should be > good enough to run most Java programs. The VectorAPI and ForeignAPI features > are not supported for now. Support for vector operations is experimental, we > need to do more testing for this part. We've provided full build instructions > [4], but we'll help you if you get stuck. Aleksey Shipilev is building > riscv-port-branch nightlies here [5]. We want people to try it out. > > We intend to continuously rebase the source code to the latest JDK mainline, and > then, after a round of in-project reviews, suggest it for integration into JDK > mainline. If this project is approved, I believe we still have time to submit > the integration JEP targeting JDK 18. We would welcome your advice and > guidance about this. > > We will consider 17u and 11u backports, after JDK mainline integration is done. > This, of course, depends on whether the 17u and 11u maintainers would approve > such backport. > > Fei Yang has been working on OpenJDK for aarch64 port project since year 2015 > and is an OpenJDK committer [6]. He is currently a major developer for OpenJDK > RISC-V port and has reviewed most of the code changes internally. Previously, > he is also a GCC committer [7] and has contributed various performance and > bugfixes since year 2013. > > The proposed initial set of reviewers are: > > Fei Yang > Aleksey Shipilev > Edward Nevill > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > Only current OpenJDK Members [8] are eligible to vote on this > motion. Votes must be cast in the open on the discuss list. > Replying to this message is sufficient if your mail program > honors the Reply-To header. > > For Lazy Consensus voting instructions, see [9]. > > Fei Yang > > [1] https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html > [2] https://github.com/riscv/riscv-isa-manual > [3] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf > [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > [5] https://builds.shipilev.net/openjdk-jdk-riscv > [6] http://openjdk.java.net/census#fyang > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > [8] http://openjdk.java.net/census#members > [9] http://openjdk.java.net/projects/#new-project-vote From magnus.ihse.bursie at oracle.com Tue Oct 12 21:32:20 2021 From: magnus.ihse.bursie at oracle.com (Magnus Ihse Bursie) Date: Tue, 12 Oct 2021 23:32:20 +0200 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: <745e5e2d-8d9d-0c1f-34e1-eca59cd7102f@oracle.com> Vote: yes /Magnus On 2021-10-11 04:39, Yangfei (Felix) wrote: > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. > > The goal of the project will be to provide a full featured port of OpenJDK > on the RISC-V platform. The current project would only target Linux. RISC-V > ISA is actually a family of related ISAs of which there are currently four > base ISAs [2]. Those base ISAs can be combined with a set of standard > extensions. RV64G and RV32G are defined as general-purpose ISAs. This port > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for > vector operations [3]. And the implementation will be fully compatible with > RISC-V ISA specifications. This port may support other ISA variants like > RV32G depending on community interest. > > We (Huawei Technologies) already have a complete (i.e. template interpreter, > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent snapshot > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should be > good enough to run most Java programs. The VectorAPI and ForeignAPI features > are not supported for now. Support for vector operations is experimental, we > need to do more testing for this part. We've provided full build instructions > [4], but we'll help you if you get stuck. Aleksey Shipilev is building > riscv-port-branch nightlies here [5]. We want people to try it out. > > We intend to continuously rebase the source code to the latest JDK mainline, and > then, after a round of in-project reviews, suggest it for integration into JDK > mainline. If this project is approved, I believe we still have time to submit > the integration JEP targeting JDK 18. We would welcome your advice and > guidance about this. > > We will consider 17u and 11u backports, after JDK mainline integration is done. > This, of course, depends on whether the 17u and 11u maintainers would approve > such backport. > > Fei Yang has been working on OpenJDK for aarch64 port project since year 2015 > and is an OpenJDK committer [6]. He is currently a major developer for OpenJDK > RISC-V port and has reviewed most of the code changes internally. Previously, > he is also a GCC committer [7] and has contributed various performance and > bugfixes since year 2013. > > The proposed initial set of reviewers are: > > Fei Yang > Aleksey Shipilev > Edward Nevill > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > Only current OpenJDK Members [8] are eligible to vote on this > motion. Votes must be cast in the open on the discuss list. > Replying to this message is sufficient if your mail program > honors the Reply-To header. > > For Lazy Consensus voting instructions, see [9]. > > Fei Yang > > [1] https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html > [2] https://github.com/riscv/riscv-isa-manual > [3] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf > [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > [5] https://builds.shipilev.net/openjdk-jdk-riscv > [6] http://openjdk.java.net/census#fyang > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > [8] http://openjdk.java.net/census#members > [9] http://openjdk.java.net/projects/#new-project-vote From david.holmes at oracle.com Wed Oct 13 01:13:33 2021 From: david.holmes at oracle.com (David Holmes) Date: Wed, 13 Oct 2021 11:13:33 +1000 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: Vote: yes David On 11/10/2021 12:39 pm, Yangfei (Felix) wrote: > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. > > The goal of the project will be to provide a full featured port of OpenJDK > on the RISC-V platform. The current project would only target Linux. RISC-V > ISA is actually a family of related ISAs of which there are currently four > base ISAs [2]. Those base ISAs can be combined with a set of standard > extensions. RV64G and RV32G are defined as general-purpose ISAs. This port > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for > vector operations [3]. And the implementation will be fully compatible with > RISC-V ISA specifications. This port may support other ISA variants like > RV32G depending on community interest. > > We (Huawei Technologies) already have a complete (i.e. template interpreter, > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent snapshot > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should be > good enough to run most Java programs. The VectorAPI and ForeignAPI features > are not supported for now. Support for vector operations is experimental, we > need to do more testing for this part. We've provided full build instructions > [4], but we'll help you if you get stuck. Aleksey Shipilev is building > riscv-port-branch nightlies here [5]. We want people to try it out. > > We intend to continuously rebase the source code to the latest JDK mainline, and > then, after a round of in-project reviews, suggest it for integration into JDK > mainline. If this project is approved, I believe we still have time to submit > the integration JEP targeting JDK 18. We would welcome your advice and > guidance about this. > > We will consider 17u and 11u backports, after JDK mainline integration is done. > This, of course, depends on whether the 17u and 11u maintainers would approve > such backport. > > Fei Yang has been working on OpenJDK for aarch64 port project since year 2015 > and is an OpenJDK committer [6]. He is currently a major developer for OpenJDK > RISC-V port and has reviewed most of the code changes internally. Previously, > he is also a GCC committer [7] and has contributed various performance and > bugfixes since year 2013. > > The proposed initial set of reviewers are: > > Fei Yang > Aleksey Shipilev > Edward Nevill > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > Only current OpenJDK Members [8] are eligible to vote on this > motion. Votes must be cast in the open on the discuss list. > Replying to this message is sufficient if your mail program > honors the Reply-To header. > > For Lazy Consensus voting instructions, see [9]. > > Fei Yang > > [1] https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html > [2] https://github.com/riscv/riscv-isa-manual > [3] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf > [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > [5] https://builds.shipilev.net/openjdk-jdk-riscv > [6] http://openjdk.java.net/census#fyang > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > [8] http://openjdk.java.net/census#members > [9] http://openjdk.java.net/projects/#new-project-vote > From Alan.Bateman at oracle.com Wed Oct 13 07:01:33 2021 From: Alan.Bateman at oracle.com (Alan Bateman) Date: Wed, 13 Oct 2021 08:01:33 +0100 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: Vote: yes From aph-open at littlepinkcloud.com Wed Oct 13 07:15:50 2021 From: aph-open at littlepinkcloud.com (Andrew Haley) Date: Wed, 13 Oct 2021 08:15:50 +0100 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: Vote: yes On 10/11/21 03:39, Yangfei (Felix) wrote: > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. > > The goal of the project will be to provide a full featured port of OpenJDK > on the RISC-V platform. The current project would only target Linux. RISC-V > ISA is actually a family of related ISAs of which there are currently four > base ISAs [2]. Those base ISAs can be combined with a set of standard > extensions. RV64G and RV32G are defined as general-purpose ISAs. This port > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for > vector operations [3]. And the implementation will be fully compatible with > RISC-V ISA specifications. This port may support other ISA variants like > RV32G depending on community interest. > > We (Huawei Technologies) already have a complete (i.e. template interpreter, > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent snapshot > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should be > good enough to run most Java programs. The VectorAPI and ForeignAPI features > are not supported for now. Support for vector operations is experimental, we > need to do more testing for this part. We've provided full build instructions > [4], but we'll help you if you get stuck. Aleksey Shipilev is building > riscv-port-branch nightlies here [5]. We want people to try it out. > > We intend to continuously rebase the source code to the latest JDK mainline, and > then, after a round of in-project reviews, suggest it for integration into JDK > mainline. If this project is approved, I believe we still have time to submit > the integration JEP targeting JDK 18. We would welcome your advice and > guidance about this. > > We will consider 17u and 11u backports, after JDK mainline integration is done. > This, of course, depends on whether the 17u and 11u maintainers would approve > such backport. > > Fei Yang has been working on OpenJDK for aarch64 port project since year 2015 > and is an OpenJDK committer [6]. He is currently a major developer for OpenJDK > RISC-V port and has reviewed most of the code changes internally. Previously, > he is also a GCC committer [7] and has contributed various performance and > bugfixes since year 2013. > > The proposed initial set of reviewers are: > > Fei Yang > Aleksey Shipilev > Edward Nevill > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > Only current OpenJDK Members [8] are eligible to vote on this > motion. Votes must be cast in the open on the discuss list. > Replying to this message is sufficient if your mail program > honors the Reply-To header. > > For Lazy Consensus voting instructions, see [9]. > > Fei Yang > > [1] https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html > [2] https://github.com/riscv/riscv-isa-manual > [3] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf > [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > [5] https://builds.shipilev.net/openjdk-jdk-riscv > [6] http://openjdk.java.net/census#fyang > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > [8] http://openjdk.java.net/census#members > [9] http://openjdk.java.net/projects/#new-project-vote > -- Andrew Haley (he/him) Java Platform Lead Engineer Red Hat UK Ltd. https://keybase.io/andrewhaley EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671 From per.liden at oracle.com Wed Oct 13 08:58:08 2021 From: per.liden at oracle.com (Per Liden) Date: Wed, 13 Oct 2021 10:58:08 +0200 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: Vote: yes /Per On 10/11/21 04:39, Yangfei (Felix) wrote: > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. > > The goal of the project will be to provide a full featured port of OpenJDK > on the RISC-V platform. The current project would only target Linux. RISC-V > ISA is actually a family of related ISAs of which there are currently four > base ISAs [2]. Those base ISAs can be combined with a set of standard > extensions. RV64G and RV32G are defined as general-purpose ISAs. This port > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for > vector operations [3]. And the implementation will be fully compatible with > RISC-V ISA specifications. This port may support other ISA variants like > RV32G depending on community interest. > > We (Huawei Technologies) already have a complete (i.e. template interpreter, > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent snapshot > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should be > good enough to run most Java programs. The VectorAPI and ForeignAPI features > are not supported for now. Support for vector operations is experimental, we > need to do more testing for this part. We've provided full build instructions > [4], but we'll help you if you get stuck. Aleksey Shipilev is building > riscv-port-branch nightlies here [5]. We want people to try it out. > > We intend to continuously rebase the source code to the latest JDK mainline, and > then, after a round of in-project reviews, suggest it for integration into JDK > mainline. If this project is approved, I believe we still have time to submit > the integration JEP targeting JDK 18. We would welcome your advice and > guidance about this. > > We will consider 17u and 11u backports, after JDK mainline integration is done. > This, of course, depends on whether the 17u and 11u maintainers would approve > such backport. > > Fei Yang has been working on OpenJDK for aarch64 port project since year 2015 > and is an OpenJDK committer [6]. He is currently a major developer for OpenJDK > RISC-V port and has reviewed most of the code changes internally. Previously, > he is also a GCC committer [7] and has contributed various performance and > bugfixes since year 2013. > > The proposed initial set of reviewers are: > > Fei Yang > Aleksey Shipilev > Edward Nevill > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > Only current OpenJDK Members [8] are eligible to vote on this > motion. Votes must be cast in the open on the discuss list. > Replying to this message is sufficient if your mail program > honors the Reply-To header. > > For Lazy Consensus voting instructions, see [9]. > > Fei Yang > > [1] https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html > [2] https://github.com/riscv/riscv-isa-manual > [3] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf > [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > [5] https://builds.shipilev.net/openjdk-jdk-riscv > [6] http://openjdk.java.net/census#fyang > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > [8] http://openjdk.java.net/census#members > [9] http://openjdk.java.net/projects/#new-project-vote > From ChrisPhi at LGonQn.Org Wed Oct 13 13:12:28 2021 From: ChrisPhi at LGonQn.Org (Chris Phillips) Date: Wed, 13 Oct 2021 09:12:28 -0400 Subject: CFV: New Project: RISC-V Port In-Reply-To: References: Message-ID: <225dc64f-ac30-9e8f-c8e5-df836a1aa0cf@LGonQn.Org> Hi< Vote: Yes Cheers! ChrisPhi From richard.reingruber at sap.com Wed Oct 13 14:05:22 2021 From: richard.reingruber at sap.com (Reingruber, Richard) Date: Wed, 13 Oct 2021 14:05:22 +0000 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: Vote: yes Richard. -----Original Message----- From: announce On Behalf Of Yangfei (Felix) Sent: Montag, 11. Oktober 2021 04:40 To: announce at openjdk.java.net Subject: CFV: New Project: RISC-V Port I hereby propose the creation of the "RISC-V Port" Project with Fei Yang as the Lead and Porters Group as the sponsoring group [1]. The goal of the project will be to provide a full featured port of OpenJDK on the RISC-V platform. The current project would only target Linux. RISC-V ISA is actually a family of related ISAs of which there are currently four base ISAs [2]. Those base ISAs can be combined with a set of standard extensions. RV64G and RV32G are defined as general-purpose ISAs. This port will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for vector operations [3]. And the implementation will be fully compatible with RISC-V ISA specifications. This port may support other ISA variants like RV32G depending on community interest. We (Huawei Technologies) already have a complete (i.e. template interpreter, C1 and C2 JIT) RISC-V port. This work is based on reasonably recent snapshot of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should be good enough to run most Java programs. The VectorAPI and ForeignAPI features are not supported for now. Support for vector operations is experimental, we need to do more testing for this part. We've provided full build instructions [4], but we'll help you if you get stuck. Aleksey Shipilev is building riscv-port-branch nightlies here [5]. We want people to try it out. We intend to continuously rebase the source code to the latest JDK mainline, and then, after a round of in-project reviews, suggest it for integration into JDK mainline. If this project is approved, I believe we still have time to submit the integration JEP targeting JDK 18. We would welcome your advice and guidance about this. We will consider 17u and 11u backports, after JDK mainline integration is done. This, of course, depends on whether the 17u and 11u maintainers would approve such backport. Fei Yang has been working on OpenJDK for aarch64 port project since year 2015 and is an OpenJDK committer [6]. He is currently a major developer for OpenJDK RISC-V port and has reviewed most of the code changes internally. Previously, he is also a GCC committer [7] and has contributed various performance and bugfixes since year 2013. The proposed initial set of reviewers are: Fei Yang Aleksey Shipilev Edward Nevill Votes are due by 9:00 UTC on Monday 25, October 2021 Only current OpenJDK Members [8] are eligible to vote on this motion. Votes must be cast in the open on the discuss list. Replying to this message is sufficient if your mail program honors the Reply-To header. For Lazy Consensus voting instructions, see [9]. Fei Yang [1] https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html [2] https://github.com/riscv/riscv-isa-manual [3] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md [5] https://builds.shipilev.net/openjdk-jdk-riscv [6] http://openjdk.java.net/census#fyang [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS [8] http://openjdk.java.net/census#members [9] http://openjdk.java.net/projects/#new-project-vote From weijun.wang at oracle.com Wed Oct 13 14:14:53 2021 From: weijun.wang at oracle.com (Wei-Jun Wang) Date: Wed, 13 Oct 2021 14:14:53 +0000 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: Vote: yes --Weijun > On Oct 10, 2021, at 10:39 PM, Yangfei (Felix) wrote: > > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. From christoph.langer at sap.com Sat Oct 16 21:53:15 2021 From: christoph.langer at sap.com (Langer, Christoph) Date: Sat, 16 Oct 2021 21:53:15 +0000 Subject: CFV: New Project: RISC-V Port In-Reply-To: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: Vote:yes /Christoph > -----Original Message----- > From: announce On Behalf Of Yangfei > (Felix) > Sent: Montag, 11. Oktober 2021 04:40 > To: announce at openjdk.java.net > Subject: CFV: New Project: RISC-V Port > > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > as the Lead and Porters Group as the sponsoring group [1]. > > The goal of the project will be to provide a full featured port of OpenJDK > on the RISC-V platform. The current project would only target Linux. RISC-V > ISA is actually a family of related ISAs of which there are currently four > base ISAs [2]. Those base ISAs can be combined with a set of standard > extensions. RV64G and RV32G are defined as general-purpose ISAs. This > port > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for > vector operations [3]. And the implementation will be fully compatible with > RISC-V ISA specifications. This port may support other ISA variants like > RV32G depending on community interest. > > We (Huawei Technologies) already have a complete (i.e. template > interpreter, > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent snapshot > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it > should be > good enough to run most Java programs. The VectorAPI and ForeignAPI > features > are not supported for now. Support for vector operations is experimental, > we > need to do more testing for this part. We've provided full build instructions > [4], but we'll help you if you get stuck. Aleksey Shipilev is building > riscv-port-branch nightlies here [5]. We want people to try it out. > > We intend to continuously rebase the source code to the latest JDK mainline, > and > then, after a round of in-project reviews, suggest it for integration into JDK > mainline. If this project is approved, I believe we still have time to submit > the integration JEP targeting JDK 18. We would welcome your advice and > guidance about this. > > We will consider 17u and 11u backports, after JDK mainline integration is > done. > This, of course, depends on whether the 17u and 11u maintainers would > approve > such backport. > > Fei Yang has been working on OpenJDK for aarch64 port project since year > 2015 > and is an OpenJDK committer [6]. He is currently a major developer for > OpenJDK > RISC-V port and has reviewed most of the code changes internally. > Previously, > he is also a GCC committer [7] and has contributed various performance and > bugfixes since year 2013. > > The proposed initial set of reviewers are: > > Fei Yang > Aleksey Shipilev > Edward Nevill > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > Only current OpenJDK Members [8] are eligible to vote on this > motion. Votes must be cast in the open on the discuss list. > Replying to this message is sufficient if your mail program > honors the Reply-To header. > > For Lazy Consensus voting instructions, see [9]. > > Fei Yang > > [1] https://mail.openjdk.java.net/pipermail/discuss/2021- > October/005964.html > [2] https://github.com/riscv/riscv-isa-manual > [3] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v- > spec-1.0.pdf > [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > [5] https://builds.shipilev.net/openjdk-jdk-riscv > [6] http://openjdk.java.net/census#fyang > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > [8] http://openjdk.java.net/census#members > [9] http://openjdk.java.net/projects/#new-project-vote From neugens.limasoftware at gmail.com Sat Oct 16 22:36:54 2021 From: neugens.limasoftware at gmail.com (Mario Torre) Date: Sun, 17 Oct 2021 00:36:54 +0200 Subject: CFV: New Project: RISC-V Port In-Reply-To: References: <4be2e8795c2d45ab98770df45f1e5a9e@huawei.com> Message-ID: <756196b1-bea8-46de-9e41-fddd77e45f77@Canary> Vote: yes Cheers, Mario ? Mario Torre Java Champion and OpenJDK contributor PGP Key: 0BAB254E Fingerprint: AB1C 7C6F 7181 895F E581 93A9 C6B8 A242 0BAB 254E Twitter: @neugens Web: https://www.mario-torre.eu/ Music: https://mario-torre.bandcamp.com/ > On Saturday, Oct 16, 2021 at 23:53, Langer Christoph wrote: > Vote:yes > > /Christoph > > > -----Original Message----- > > From: announce On Behalf Of Yangfei > > (Felix) > > Sent: Montag, 11. Oktober 2021 04:40 > > To: announce at openjdk.java.net > > Subject: CFV: New Project: RISC-V Port > > > > I hereby propose the creation of the "RISC-V Port" Project with Fei Yang > > as the Lead and Porters Group as the sponsoring group [1]. > > > > The goal of the project will be to provide a full featured port of OpenJDK > > on the RISC-V platform. The current project would only target Linux. RISC-V > > ISA is actually a family of related ISAs of which there are currently four > > base ISAs [2]. Those base ISAs can be combined with a set of standard > > extensions. RV64G and RV32G are defined as general-purpose ISAs. This > > port > > will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for > > vector operations [3]. And the implementation will be fully compatible with > > RISC-V ISA specifications. This port may support other ISA variants like > > RV32G depending on community interest. > > > > We (Huawei Technologies) already have a complete (i.e. template > > interpreter, > > C1 and C2 JIT) RISC-V port. This work is based on reasonably recent snapshot > > of JDK mainline and resides in the riscv-port-branch of jdk-sandbox: > > > > https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch > > > > We've passed JTReg tests on QEMU and HiFive Unleashed board. So it > > should be > > good enough to run most Java programs. The VectorAPI and ForeignAPI > > features > > are not supported for now. Support for vector operations is experimental, > > we > > need to do more testing for this part. We've provided full build instructions > > [4], but we'll help you if you get stuck. Aleksey Shipilev is building > > riscv-port-branch nightlies here [5]. We want people to try it out. > > > > We intend to continuously rebase the source code to the latest JDK mainline, > > and > > then, after a round of in-project reviews, suggest it for integration into JDK > > mainline. If this project is approved, I believe we still have time to submit > > the integration JEP targeting JDK 18. We would welcome your advice and > > guidance about this. > > > > We will consider 17u and 11u backports, after JDK mainline integration is > > done. > > This, of course, depends on whether the 17u and 11u maintainers would > > approve > > such backport. > > > > Fei Yang has been working on OpenJDK for aarch64 port project since year > > 2015 > > and is an OpenJDK committer [6]. He is currently a major developer for > > OpenJDK > > RISC-V port and has reviewed most of the code changes internally. > > Previously, > > he is also a GCC committer [7] and has contributed various performance and > > bugfixes since year 2013. > > > > The proposed initial set of reviewers are: > > > > Fei Yang > > Aleksey Shipilev > > Edward Nevill > > > > Votes are due by 9:00 UTC on Monday 25, October 2021 > > > > Only current OpenJDK Members [8] are eligible to vote on this > > motion. Votes must be cast in the open on the discuss list. > > Replying to this message is sufficient if your mail program > > honors the Reply-To header. > > > > For Lazy Consensus voting instructions, see [9]. > > > > Fei Yang > > > > [1] https://mail.openjdk.java.net/pipermail/discuss/2021- > > October/005964.html > > [2] https://github.com/riscv/riscv-isa-manual > > [3] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v- > > spec-1.0.pdf > > [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md > > [5] https://builds.shipilev.net/openjdk-jdk-riscv > > [6] http://openjdk.java.net/census#fyang > > [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS > > [8] http://openjdk.java.net/census#members > > [9] http://openjdk.java.net/projects/#new-project-vote