CFV: New Project: RISC-V Port

[Thomas Stüfe]

Vote: yes

On Mon, Oct 11, 2021 at 8:27 PM Yangfei (Felix) <felix.yang at huawei.com>
wrote:

> I hereby propose the creation of the "RISC-V Port" Project with Fei Yang
> as the Lead and Porters Group as the sponsoring group [1].
>
> The goal of the project will be to provide a full featured port of OpenJDK
> on the RISC-V platform.  The current project would only target Linux.
> RISC-V
> ISA is actually a family of related ISAs of which there are currently four
> base ISAs [2].  Those base ISAs can be combined with a set of standard
> extensions. RV64G and RV32G are defined as general-purpose ISAs.  This port
> will support RV64GV , i.e., RV64G ISA plus the "V" standard extension for
> vector operations [3].  And the implementation will be fully compatible
> with
> RISC-V ISA specifications.  This port may support other ISA variants like
> RV32G depending on community interest.
>
> We (Huawei Technologies) already have a complete (i.e. template
> interpreter,
> C1 and C2 JIT) RISC-V port.  This work is based on reasonably recent
> snapshot
> of JDK mainline and resides in the riscv-port-branch of jdk-sandbox:
>
> https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch
>
> We've passed JTReg tests on QEMU and HiFive Unleashed board.  So it should
> be
> good enough to run most Java programs.  The VectorAPI and ForeignAPI
> features
> are not supported for now.  Support for vector operations is experimental,
> we
> need to do more testing for this part.  We've provided full build
> instructions
> [4], but we'll help you if you get stuck.  Aleksey Shipilev is building
> riscv-port-branch nightlies here [5].  We want people to try it out.
>
> We intend to continuously rebase the source code to the latest JDK
> mainline, and
> then, after a round of in-project reviews, suggest it for integration into
> JDK
> mainline.  If this project is approved, I believe we still have time to
> submit
> the integration JEP targeting JDK 18.  We would welcome your advice and
> guidance about this.
>
> We will consider 17u and 11u backports, after JDK mainline integration is
> done.
> This, of course, depends on whether the 17u and 11u maintainers would
> approve
> such backport.
>
> Fei Yang has been working on OpenJDK for aarch64 port project since year
> 2015
> and is an OpenJDK committer [6].  He is currently a major developer for
> OpenJDK
> RISC-V port and has reviewed most of the code changes internally.
> Previously,
> he is also a GCC committer [7] and has contributed various performance and
> bugfixes since year 2013.
>
> The proposed initial set of reviewers are:
>
> Fei Yang
> Aleksey Shipilev
> Edward Nevill
>
> Votes are due by 9:00 UTC on Monday 25, October 2021
>
> Only current OpenJDK Members [8] are eligible to vote on this
> motion.  Votes must be cast in the open on the discuss list.
> Replying to this message is sufficient if your mail program
> honors the Reply-To header.
>
> For Lazy Consensus voting instructions, see [9].
>
> Fei Yang
>
> [1]
> https://mail.openjdk.java.net/pipermail/discuss/2021-October/005964.html
> [2] https://github.com/riscv/riscv-isa-manual
> [3]
> https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf
> [4] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md
> [5] https://builds.shipilev.net/openjdk-jdk-riscv
> [6] http://openjdk.java.net/census#fyang
> [7] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS
> [8] http://openjdk.java.net/census#members
> [9] http://openjdk.java.net/projects/#new-project-vote
>