Call for Discussion: New Project: RISC-V Port

[Yangfei (Felix)]

Hi,

We would like to propose a new project called "RISC-V Port".

The goal of the project will be to provide a full featured port of OpenJDK on
the RISC-V platform. The current project would only target Linux. RISC-V ISA is
actually a family of related ISAs of which there are currently four base ISAs [1].
Those base ISAs can be combined with a set of standard extensions. RV64G and
RV32G are defined as general-purpose ISAs. This port will support RV64GV, i.e.,
RV64G ISA plus the "V" standard extension for vector operations [2]. And the
implementation will be fully compatible with RISC-V ISA specifications. This port
may support other ISA variants like RV32G depending on community interest.

We (Huawei Technologies) already have a complete (i.e. template interpreter, C1 and
C2 JIT) RISC-V port. This work is based on a snapshot of JDK main-line on May 10, 2021
and has been pushed to the riscv-port-branch of jdk-sandbox:

https://github.com/openjdk/jdk-sandbox/tree/riscv-port-branch

We've passed JTReg tests on QEMU and HiFive Unleashed board. So it should be good
enough to run most Java programs. The VectorAPI and ForeignAPI features are not
supported for now. Support for vector operations is experimental, we need to do more
testing for this part. We've provided full build instructions [3], but we'll help you
if you get stuck. Aleksey Shipilev is building riscv-port-branch nightlies here [4].
We want people to try it out.

We intend to rebase the source code to the latest JDK mainline, and then, after a round
of in-project reviews, suggest it for integration into JDK mainline. If this project
is approved, I believe we still have time to submit the integration JEP targeting JDK 18.
We would welcome your advice and guidance about this.

We will consider 17u and 11u backports, after JDK mainline integration is done. This,
of course, depends on whether the 17u and 11u maintainers would approve such backport.

I propose myself, Fei Yang as a Project Lead of this new project. If you're interested
or want to be the committer, please drop me a message.

I have been working on OpenJDK for aarch64 port project since year 2015 and is an
OpenJDK committer [5]. I am currently a major developer for OpenJDK RISC-V port
and has reviewed most of the code changes internally. Previously, I am also a GCC
committer [6] and has contributed various performance and bugfixes since year 2013.

The proposed initial set of reviewers are:

Fei Yang         <felix.yang at huawei.com>
Aleksey Shipilev <shade at redhat.com>
Edward Nevill    <edward.nevill at gmail.com>

Other contrbutors who are not listed on OpenJDK Census include:

Yadong Wang   <yadonn.wang at huawei.com>
Feilong Jiang <jiangfeilong at huawei.com>
Taiping Guo   <guotaiping at huawei.com>
Yanhong Zhu   <zhuyanhong at huawei.com>
Kuai Wei      <kuaiwei.kw at alibaba-inc.com>
Xiaolin Zheng <yunyao.zxl at alibaba-inc.com>

These people will be nominated to the proper community roles starting from Authors
once this project is formed.

Comments, expressions of interest etc. are welcome.

Thanks,
Felix

[1] https://github.com/riscv/riscv-isa-manual
[2] https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf
[3] http://cr.openjdk.java.net/~fyang/openjdk-riscv-port/BuildRISCVJDK.md
[4] https://builds.shipilev.net/openjdk-jdk-riscv
[5] http://openjdk.java.net/census#fyang
[6] https://github.com/gcc-mirror/gcc/blob/master/MAINTAINERS