changeset in /hg/icedtea: 2007-12-12 Gary Benson <gbenson at redh...
Gary Benson
gbenson at redhat.com
Wed Dec 12 07:44:59 PST 2007
changeset 5e6aacdf3f50 in /hg/icedtea
details: http://icedtea.classpath.org/hg/icedtea?cmd=changeset;node=5e6aacdf3f50
description:
2007-12-12 Gary Benson <gbenson at redhat.com>
* ports/hotspot/src/cpu/ppc/vm/disassembler_ppc.hpp
(decode): Implement.
* ports/hotspot/src/cpu/ppc/vm/disassembler_ppc.cpp
(decode): Likewise.
* ports/hotspot/src/cpu/ppc/vm/assembler_ppc.hpp
(disassemble): Remove.
* ports/hotspot/src/cpu/ppc/vm/assembler_ppc.cpp
(disassemble): Likewise.
diffstat:
5 files changed, 703 insertions(+), 58 deletions(-)
ChangeLog | 11
ports/hotspot/src/cpu/ppc/vm/assembler_ppc.cpp | 39 -
ports/hotspot/src/cpu/ppc/vm/assembler_ppc.hpp | 5
ports/hotspot/src/cpu/ppc/vm/disassembler_ppc.cpp | 686 +++++++++++++++++++++
ports/hotspot/src/cpu/ppc/vm/disassembler_ppc.hpp | 20
diffs (truncated from 804 to 500 lines):
diff -r b2f47e545447 -r 5e6aacdf3f50 ChangeLog
--- a/ChangeLog Wed Dec 12 10:41:44 2007 -0500
+++ b/ChangeLog Wed Dec 12 10:44:53 2007 -0500
@@ -1,3 +1,14 @@ 2007-12-12 Gary Benson <gbenson at redhat
+2007-12-12 Gary Benson <gbenson at redhat.com>
+
+ * ports/hotspot/src/cpu/ppc/vm/disassembler_ppc.hpp
+ (decode): Implement.
+ * ports/hotspot/src/cpu/ppc/vm/disassembler_ppc.cpp
+ (decode): Likewise.
+ * ports/hotspot/src/cpu/ppc/vm/assembler_ppc.hpp
+ (disassemble): Remove.
+ * ports/hotspot/src/cpu/ppc/vm/assembler_ppc.cpp
+ (disassemble): Likewise.
+
2007-12-12 Gary Benson <gbenson at redhat.com>
* ports/hotspot/src/cpu/ppc/vm/assembler_ppc.hpp
diff -r b2f47e545447 -r 5e6aacdf3f50 ports/hotspot/src/cpu/ppc/vm/assembler_ppc.cpp
--- a/ports/hotspot/src/cpu/ppc/vm/assembler_ppc.cpp Wed Dec 12 10:41:44 2007 -0500
+++ b/ports/hotspot/src/cpu/ppc/vm/assembler_ppc.cpp Wed Dec 12 10:44:53 2007 -0500
@@ -649,49 +649,10 @@ void Assembler::pd_patch_instruction(add
}
#ifndef PRODUCT
-
void Assembler::pd_print_patched_instruction(address branch)
{
Unimplemented();
}
-
-void Assembler::disassemble(const char *what, address start, address end)
-{
- const char *fmt = "/tmp/aztec-%d.%c";
- char c_file[BUFSIZ], o_file[BUFSIZ];
- sprintf(c_file, fmt, getpid(), 'c');
- sprintf(o_file, fmt, getpid(), 'o');
-
- FILE *fp = fopen(c_file, "w");
- if (fp == NULL)
- fatal2("%s:%d: can't write file", __FILE__, __LINE__);
-
- fputs("unsigned char start[] = {", fp);
- for (address a = start; a < end; a++) {
- if (a != start)
- fputc(',', fp);
- fprintf(fp, "0x%02x", *a);
- }
- fputs("};\n", fp);
- fclose(fp);
-
- char cmd[BUFSIZ];
- sprintf(cmd, "gcc -m%d -c %s -o %s", wordSize * 8, c_file, o_file);
- if (system(cmd) != 0)
- fatal2("%s:%d: can't compile file", __FILE__, __LINE__);
-
- printf("%s: %p-%p:\n", what, start, end);
- fflush(stdout);
- sprintf(cmd, "objdump -D -j .data %s | grep '^....:'", o_file);
- if (system(cmd) != 0)
- fatal2("%s:%d: can't disassemble file", __FILE__, __LINE__);
- putchar('\n');
- fflush(stdout);
-
- unlink(c_file);
- unlink(o_file);
-}
-
#endif // PRODUCT
// 32-bit ABI:
diff -r b2f47e545447 -r 5e6aacdf3f50 ports/hotspot/src/cpu/ppc/vm/assembler_ppc.hpp
--- a/ports/hotspot/src/cpu/ppc/vm/assembler_ppc.hpp Wed Dec 12 10:41:44 2007 -0500
+++ b/ports/hotspot/src/cpu/ppc/vm/assembler_ppc.hpp Wed Dec 12 10:44:53 2007 -0500
@@ -231,11 +231,6 @@ class Assembler : public AbstractAssembl
#ifndef PRODUCT
static void pd_print_patched_instruction(address branch);
#endif // PRODUCT
-
- // Disassemble a region of memory to stdout
-#ifndef PRODUCT
- static void disassemble(const char *what, address start, address end);
-#endif // PRODUCT
};
diff -r b2f47e545447 -r 5e6aacdf3f50 ports/hotspot/src/cpu/ppc/vm/disassembler_ppc.cpp
--- a/ports/hotspot/src/cpu/ppc/vm/disassembler_ppc.cpp Wed Dec 12 10:41:44 2007 -0500
+++ b/ports/hotspot/src/cpu/ppc/vm/disassembler_ppc.cpp Wed Dec 12 10:44:53 2007 -0500
@@ -0,0 +1,686 @@
+/*
+ * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
+ * Copyright 2007 Red Hat, Inc.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ *
+ */
+
+#include "incls/_precompiled.incl"
+#include "incls/_disassembler_ppc.cpp.incl"
+
+#ifndef PRODUCT
+class InstructionParser {
+ private:
+ intptr_t _addr;
+ int _instruction;
+ int _bits;
+
+ public:
+ InstructionParser(address addr)
+ : _addr((intptr_t) addr),
+ _instruction(*(int *) addr),
+ _bits(26) {}
+
+ intptr_t pc() const {
+ return _addr;
+ }
+
+ int instruction() const {
+ return _instruction;
+ }
+
+ int opcode() const {
+ return (_instruction >> 26) & 0x3f;
+ }
+
+ int extended_opcode() const {
+ switch(opcode()) {
+ case 19:
+ case 31:
+ case 63:
+ return (_instruction >> 1) & 0x3ff;
+
+ case 30:
+ return (_instruction >> 2) & 7;
+
+ case 58:
+ case 62:
+ return _instruction & 3;
+
+ default:
+ return -1;
+ }
+ }
+
+ int read(int nbits) {
+ _bits -= nbits;
+ assert(_bits >= 0, "oops");
+ return (_instruction >> _bits) & ((1 << nbits) - 1);
+ }
+
+ int read_signed(int nbits) {
+ int v = read(nbits);
+ if (v & (1 << (nbits - 1)))
+ v |= ~((1 << nbits) - 1);
+ return v;
+ }
+
+ int read_reg() {
+ return read(5);
+ }
+
+ int read_xo() {
+ int xo = read(10);
+ assert(xo == extended_opcode(), "should be");
+ return xo;
+ }
+};
+
+class InstructionDefinition {
+ public:
+ typedef void (*printer_t)(InstructionParser& p,
+ const InstructionDefinition& d,
+ outputStream *st);
+ private:
+ int _opcode;
+ int _xo;
+ const char *_mnemonic;
+ printer_t _printer;
+
+ public:
+ InstructionDefinition(int opcode, const char *mn, printer_t p)
+ : _opcode(opcode), _xo(-1), _mnemonic(mn), _printer(p) {}
+
+ InstructionDefinition(int opcode, int xo, const char *mn, printer_t p)
+ : _opcode(opcode), _xo(xo), _mnemonic(mn), _printer(p) {}
+
+ int opcode() const {
+ return _opcode;
+ }
+
+ int extended_opcode() const {
+ return _xo;
+ }
+
+ const char *mnemonic() const {
+ return _mnemonic;
+ }
+
+ const printer_t printer() const {
+ return _printer;
+ }
+};
+
+#define CONDITION(BO, BI) (((BO) << 2) | ((BI) & 3))
+const char *branch_condition(int BO, int BI)
+{
+ switch (CONDITION(BO, BI)) {
+ case CONDITION(12, 0):
+ return "lt";
+
+ case CONDITION(4, 1):
+ return "le";
+
+ case CONDITION(12, 2):
+ return "eq";
+
+ case CONDITION(4, 0):
+ return "ge";
+
+ case CONDITION(12, 1):
+ return "gt";
+
+ case CONDITION(4, 2):
+ return "ne";
+
+ case CONDITION(16, 0):
+ return "dnz";
+
+ case CONDITION(20, 0):
+ return "";
+
+ default:
+ tty->print_cr("BO = %d, BI = %d", BO, BI & 3);
+ ShouldNotReachHere();
+ }
+}
+#undef CONDITION
+
+#define INSTRUCTION_PRINTER(name) \
+ static void name(InstructionParser& p, \
+ const InstructionDefinition& d, \
+ outputStream *st)
+
+// Instruction printers
+
+INSTRUCTION_PRINTER(print_B_bc)
+{
+ assert(p.opcode() == 16, "should be");
+
+ int BO = p.read(5);
+ int BI = p.read(5);
+ int BD = p.read_signed(14);
+ int AA = p.read(1);
+ int LK = p.read(1);
+
+ if (BO == 20) {
+ if (BI == 31 && BD == 1 && AA == 0 && LK == 1) {
+ st->print("mpclr");
+ return;
+ }
+ st->print_cr("BO = %d, BI = %d", BO, BI & 3);
+ ShouldNotReachHere();
+ }
+
+ const char *cond = branch_condition(BO, BI);
+ int cr = BI >> 2;
+ address tgt = (address) (p.pc() + (BD << 2));
+
+ if (cr)
+ st->print("b%s%s%s cr%d, %p", cond, LK ? "l" : "", AA ? "a" : "", cr, tgt);
+ else
+ st->print("b%s%s%s %p", cond, LK ? "l" : "", AA ? "a" : "", tgt);
+}
+
+INSTRUCTION_PRINTER(print_I_b)
+{
+ assert(p.opcode() == 18, "should be");
+
+ int LI = p.read_signed(24);
+ int AA = p.read(1);
+ int LK = p.read(1);
+
+ address tgt = (address) (p.pc() + (LI << 2));
+
+ st->print("b%s%s %p", LK ? "l" : "", AA ? "a" : "", tgt);
+}
+
+INSTRUCTION_PRINTER(print_D_reg_reg_simm)
+{
+ int RT = p.read_reg();
+ int RA = p.read_reg();
+ int SI = p.read_signed(16);
+
+ if (RA == 0) {
+ switch (p.opcode()) {
+ case 14:
+ st->print("li r%d, %d", RT, SI);
+ return;
+
+ case 15:
+ st->print("lis r%d, %d", RT, SI);
+ return;
+ }
+ }
+
+ const char *mnemonic = d.mnemonic();
+ if (p.opcode() == 14 && SI < 0) {
+ mnemonic = "subi";
+ SI = -SI;
+ }
+
+ st->print("%s r%d, %s%d, %d", mnemonic, RT, RA ? "r" : "", RA, SI);
+}
+
+INSTRUCTION_PRINTER(print_D_reg_reg_uimm)
+{
+ int RT = p.read_reg();
+ int RA = p.read_reg();
+ int UI = p.read(16);
+
+ if (p.opcode() == 24 && RT == 0 && RA == 0 && UI == 0)
+ st->print("nop");
+ else
+ st->print("%s r%d, r%d, %d", d.mnemonic(), RA, RT, UI);
+}
+
+INSTRUCTION_PRINTER(print_D_reg_addr)
+{
+ int RT = p.read_reg();
+ int RA = p.read_reg();
+ int D = p.read_signed(16);
+
+ st->print("%s r%d, %d(%s%d)", d.mnemonic(), RT, D, RA ? "r" : "", RA);
+}
+
+INSTRUCTION_PRINTER(print_D_freg_addr)
+{
+ int FRT = p.read_reg();
+ int RA = p.read_reg();
+ int D = p.read_signed(16);
+
+ st->print("%s f%d, %d(%s%d)", d.mnemonic(), FRT, D, RA ? "r" : "", RA);
+}
+
+INSTRUCTION_PRINTER(print_DS_reg_addr)
+{
+ int RT = p.read_reg();
+ int RA = p.read_reg();
+ int DS = p.read_signed(14);
+
+ st->print("%s r%d, %d(%s%d)", d.mnemonic(), RT, DS << 2, RA ? "r" : "", RA);
+}
+
+INSTRUCTION_PRINTER(print_X_bcspr)
+{
+ assert(p.opcode() == 19, "should be");
+
+ int BO = p.read(5);
+ int BI = p.read(5);
+ int x1 = p.read(5);
+ int xo = p.read_xo();
+ int LK = p.read(1);
+
+ assert(x1 == 0, "should do");
+
+ const char *cond = branch_condition(BO, BI);
+ const char *spr;
+ switch (xo) {
+ case 16:
+ spr = "lr";
+ break;
+
+ case 528:
+ spr = "ctr";
+ break;
+
+ default:
+ st->print_cr("xo = %d", xo);
+ ShouldNotReachHere();
+ }
+
+ st->print("b%s%s%s", cond, spr, LK ? "l" : "");
+}
+
+INSTRUCTION_PRINTER(print_M)
+{
+ assert(p.opcode() == 21, "should be");
+
+ int RS = p.read_reg();
+ int RA = p.read_reg();
+ int SH = p.read(5);
+ int MB = p.read(5);
+ int ME = p.read(5);
+ int Rc = p.read(1);
+
+ if (MB == 0 && 31 - SH == ME)
+ st->print("slwi%s r%d, r%d, %d", Rc ? "." : "", RA, RS, SH);
+ else if (ME == 31 && 32 - MB == SH)
+ st->print("srwi%s r%d, r%d, %d", Rc ? "." : "", RA, RS, MB);
+ else
+ ShouldNotReachHere();
+}
+
+INSTRUCTION_PRINTER(print_MD)
+{
+ assert(p.opcode() == 30, "should be");
+
+ int RS = p.read_reg();
+ int RA = p.read_reg();
+ int shl = p.read(5);
+ int mel = p.read(5);
+ int meh = p.read(1);
+ int xo = p.read(3);
+ int shh = p.read(1);
+ int Rc = p.read(1);
+
+ int SH = shh << 5 | shl;
+ int ME = meh << 5 | mel;
+
+ if (xo == 0) {
+ if (SH = 64 - ME)
+ st->print("srdi%s r%d, r%d, %d", Rc ? "." : "", RA, RS, ME);
+ else
+ ShouldNotReachHere();
+ }
+ else if (xo == 1) {
+ if (ME == 63 - SH)
+ st->print("sldi%s r%d, r%d, %d", Rc ? "." : "", RA, RS, SH);
+ else
+ ShouldNotReachHere();
+ }
+ else
+ ShouldNotReachHere();
+}
+
+INSTRUCTION_PRINTER(print_X_reg_reg_reg)
+{
+ int RT = p.read_reg();
+ int RA = p.read_reg();
+ int RB = p.read_reg();
+ int xo = p.read_xo();
+ int Rc = p.read(1);
+
+ const char *mnemonic = d.mnemonic();
+ if (xo == 40) {
+ mnemonic = "sub";
+ int s = RA;
+ RA = RB;
+ RB = s;
+ }
+
+ st->print("%s%s r%d, r%d, r%d", mnemonic, Rc ? "." : "", RT, RA, RB);
+}
+
+INSTRUCTION_PRINTER(print_X_reg_regorzero_reg)
+{
+ int RT = p.read_reg();
+ int RA = p.read_reg();
+ int RB = p.read_reg();
+ int xo = p.read_xo();
+ int Rc = p.read(1);
+
+ const char *mnemonic = d.mnemonic();
+ if (xo == 40) {
+ mnemonic = "sub";
+ int s = RA;
+ RA = RB;
+ RB = s;
+ }
+
+ st->print("%s%s r%d, %s%d, r%d", mnemonic, Rc ? "." : "", RT,
+ RA ? "r" : "", RA, RB);
+}
+
+INSTRUCTION_PRINTER(print_X_res_regorzero_reg)
+{
+ int x1 = p.read_reg();
+ int RA = p.read_reg();
+ int RB = p.read_reg();
+ int xo = p.read_xo();
+ int Rc = p.read(1);
+
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