changeset in /hg/icedtea: 2007-11-16 Gary Benson <gbenson at redh...
Gary Benson
gbenson at redhat.com
Fri Nov 16 05:18:38 PST 2007
changeset 1f7f39188e9f in /hg/icedtea
details: http://icedtea.classpath.org/hg/icedtea?cmd=changeset;node=1f7f39188e9f
description:
2007-11-16 Gary Benson <gbenson at redhat.com>
* contrib: New directory.
* Makefile.am (EXTRA_DIST): Added the above.
* Makefile.in: Regenerated.
* contrib/templater: Imported.
diffstat:
70 files changed, 9306 insertions(+), 2 deletions(-)
ChangeLog | 8
Makefile.am | 2
Makefile.in | 2
contrib/templater/README | 2
contrib/templater/generate.py | 184 +
contrib/templater/hotspot/build/linux/makefiles/CPUS.make | 46
contrib/templater/hotspot/build/linux/platform_CPUS | 19
contrib/templater/hotspot/src/cpu/CPU/vm/assembler_CPU.cpp | 1375 +++++++++
contrib/templater/hotspot/src/cpu/CPU/vm/assembler_CPU.hpp | 408 ++
contrib/templater/hotspot/src/cpu/CPU/vm/bytecodeInterpreter_CPU.hpp | 103
contrib/templater/hotspot/src/cpu/CPU/vm/bytecodeInterpreter_CPU.inline.hpp | 281 ++
contrib/templater/hotspot/src/cpu/CPU/vm/bytecodes_CPU.cpp | 32
contrib/templater/hotspot/src/cpu/CPU/vm/bytecodes_CPU.hpp | 25
contrib/templater/hotspot/src/cpu/CPU/vm/bytes_CPU.hpp | 204 +
contrib/templater/hotspot/src/cpu/CPU/vm/codeBuffer_CPU.hpp | 27
contrib/templater/hotspot/src/cpu/CPU/vm/copy_CPU.hpp | 166 +
contrib/templater/hotspot/src/cpu/CPU/vm/cppInterpreterGenerator_CPU.hpp | 30
contrib/templater/hotspot/src/cpu/CPU/vm/cppInterpreter_CPU.cpp | 1380 ++++++++++
contrib/templater/hotspot/src/cpu/CPU/vm/cppInterpreter_CPU.hpp | 32
contrib/templater/hotspot/src/cpu/CPU/vm/debug_CPU.cpp | 32
contrib/templater/hotspot/src/cpu/CPU/vm/disassembler_CPU.hpp | 46
contrib/templater/hotspot/src/cpu/CPU/vm/dump_CPU.cpp | 37
contrib/templater/hotspot/src/cpu/CPU/vm/frame_CPU.cpp | 131
contrib/templater/hotspot/src/cpu/CPU/vm/frame_CPU.hpp | 74
contrib/templater/hotspot/src/cpu/CPU/vm/frame_CPU.inline.hpp | 195 +
contrib/templater/hotspot/src/cpu/CPU/vm/globals_CPU.hpp | 55
contrib/templater/hotspot/src/cpu/CPU/vm/icBuffer_CPU.cpp | 52
contrib/templater/hotspot/src/cpu/CPU/vm/icache_CPU.cpp | 107
contrib/templater/hotspot/src/cpu/CPU/vm/icache_CPU.hpp | 45
contrib/templater/hotspot/src/cpu/CPU/vm/interp_masm_CPU.cpp | 121
contrib/templater/hotspot/src/cpu/CPU/vm/interp_masm_CPU.hpp | 36
contrib/templater/hotspot/src/cpu/CPU/vm/interpreterGenerator_CPU.hpp | 37
contrib/templater/hotspot/src/cpu/CPU/vm/interpreterRT_CPU.cpp | 329 ++
contrib/templater/hotspot/src/cpu/CPU/vm/interpreterRT_CPU.hpp | 155 +
contrib/templater/hotspot/src/cpu/CPU/vm/interpreter_CPU.cpp | 187 +
contrib/templater/hotspot/src/cpu/CPU/vm/interpreter_CPU.hpp | 56
contrib/templater/hotspot/src/cpu/CPU/vm/javaFrameAnchor_CPU.hpp | 79
contrib/templater/hotspot/src/cpu/CPU/vm/jniFastGetField_CPU.cpp | 67
contrib/templater/hotspot/src/cpu/CPU/vm/jniTypes_CPU.hpp | 108
contrib/templater/hotspot/src/cpu/CPU/vm/jni_CPU.h | 32
contrib/templater/hotspot/src/cpu/CPU/vm/nativeInst_CPU.hpp | 170 +
contrib/templater/hotspot/src/cpu/CPU/vm/registerMap_CPU.hpp | 39
contrib/templater/hotspot/src/cpu/CPU/vm/register_CPU.cpp | 53
contrib/templater/hotspot/src/cpu/CPU/vm/register_CPU.hpp | 260 +
contrib/templater/hotspot/src/cpu/CPU/vm/register_definitions_CPU.cpp | 117
contrib/templater/hotspot/src/cpu/CPU/vm/relocInfo_CPU.cpp | 68
contrib/templater/hotspot/src/cpu/CPU/vm/relocInfo_CPU.hpp | 34
contrib/templater/hotspot/src/cpu/CPU/vm/sharedRuntime_CPU.cpp | 252 +
contrib/templater/hotspot/src/cpu/CPU/vm/stubGenerator_CPU.cpp | 524 +++
contrib/templater/hotspot/src/cpu/CPU/vm/stubRoutines_CPU.hpp | 58
contrib/templater/hotspot/src/cpu/CPU/vm/vmStructs_CPU.hpp | 52
contrib/templater/hotspot/src/cpu/CPU/vm/vm_version_CPU.hpp | 32
contrib/templater/hotspot/src/cpu/CPU/vm/vmreg_CPU.cpp | 45
contrib/templater/hotspot/src/cpu/CPU/vm/vmreg_CPU.inline.hpp | 32
contrib/templater/hotspot/src/cpu/CPU/vm/vtableStubs_CPU.cpp | 47
contrib/templater/hotspot/src/os_cpu/linux_CPU/vm/atomic_linux_CPU.inline.hpp | 162 +
contrib/templater/hotspot/src/os_cpu/linux_CPU/vm/bytes_linux_CPU.inline.hpp | 43
contrib/templater/hotspot/src/os_cpu/linux_CPU/vm/globals_linux_CPU.hpp | 43
contrib/templater/hotspot/src/os_cpu/linux_CPU/vm/linux_ppc.s | 76
contrib/templater/hotspot/src/os_cpu/linux_CPU/vm/linux_ppc64.s | 96
contrib/templater/hotspot/src/os_cpu/linux_CPU/vm/orderAccess_linux_CPU.inline.hpp | 101
contrib/templater/hotspot/src/os_cpu/linux_CPU/vm/os_linux_CPU.cpp | 313 ++
contrib/templater/hotspot/src/os_cpu/linux_CPU/vm/os_linux_CPU.hpp | 36
contrib/templater/hotspot/src/os_cpu/linux_CPU/vm/prefetch_linux_CPU.inline.hpp | 42
contrib/templater/hotspot/src/os_cpu/linux_CPU/vm/threadLS_linux_CPU.cpp | 42
contrib/templater/hotspot/src/os_cpu/linux_CPU/vm/threadLS_linux_CPU.hpp | 32
contrib/templater/hotspot/src/os_cpu/linux_CPU/vm/thread_linux_CPU.hpp | 85
contrib/templater/hotspot/src/os_cpu/linux_CPU/vm/vmStructs_linux_CPU.hpp | 45
contrib/templater/j2se/src/solaris/bin/CPUS/jvm.cfg | 44
contrib/templater/j2se/src/solaris/bin/ergo_CPU.c | 58
diffs (truncated from 9603 to 500 lines):
diff -r 53c81bc2c2cf -r 1f7f39188e9f ChangeLog
--- a/ChangeLog Thu Nov 15 10:36:40 2007 -0500
+++ b/ChangeLog Fri Nov 16 13:18:29 2007 +0000
@@ -1,3 +1,11 @@ 2007-11-15 Lillian Angel <langel at redha
+2007-11-16 Gary Benson <gbenson at redhat.com>
+
+ * contrib: New directory.
+ * Makefile.am (EXTRA_DIST): Added the above.
+ * Makefile.in: Regenerated.
+
+ * contrib/templater: Imported.
+
2007-11-15 Lillian Angel <langel at redhat.com>
* tools-copy/tools-j2se-copy-files.txt: Removed.
diff -r 53c81bc2c2cf -r 1f7f39188e9f Makefile.am
--- a/Makefile.am Thu Nov 15 10:36:40 2007 -0500
+++ b/Makefile.am Fri Nov 16 13:18:29 2007 +0000
@@ -29,7 +29,7 @@ install:
clean-copy clean-rt clean-gcjwebplugin
EXTRA_DIST = rt generated $(ICEDTEA_PATCHES) $(ICEDTEA_ECJ_PATCH) \
- gcjwebplugin.cc patches/icedtea-speed.patch tools-copy
+ gcjwebplugin.cc patches/icedtea-speed.patch tools-copy contrib
# OpenJDK build environment.
LINUX_DIR = linux-$(BUILD_ARCH_DIR)
diff -r 53c81bc2c2cf -r 1f7f39188e9f Makefile.in
--- a/Makefile.in Thu Nov 15 10:36:40 2007 -0500
+++ b/Makefile.in Fri Nov 16 13:18:29 2007 +0000
@@ -191,7 +191,7 @@ OPENJDK_DATE = 30_oct_2007
OPENJDK_DATE = 30_oct_2007
OPENJDK_MD5SUM = 7eed137c0321e0b5b75ff2d646ce0d0d
EXTRA_DIST = rt generated $(ICEDTEA_PATCHES) $(ICEDTEA_ECJ_PATCH) \
- gcjwebplugin.cc patches/icedtea-speed.patch tools-copy
+ gcjwebplugin.cc patches/icedtea-speed.patch tools-copy contrib
# OpenJDK build environment.
diff -r 53c81bc2c2cf -r 1f7f39188e9f contrib/templater/README
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/contrib/templater/README Fri Nov 16 13:18:29 2007 +0000
@@ -0,0 +1,2 @@
+Please read http://gbenson.livejournal.com/2007/11/16/
+Thank you goodbye
diff -r 53c81bc2c2cf -r 1f7f39188e9f contrib/templater/generate.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/contrib/templater/generate.py Fri Nov 16 13:18:29 2007 +0000
@@ -0,0 +1,184 @@
+import os
+import re
+
+ENDIAN, BITS, RWINDOW = 0, 1, 2
+
+cpus = {"ia64": ("little", 64, True),
+ "ppc": ("big", 32, False),
+ "ppc64": ("big", 64, False),
+ "s390": ("little", 32, False),
+ "s390x": ("little", 64, False)}
+
+modes = {"ia64": ("ia64",),
+ "ppc": ("ppc", "ppc64"),
+ "s390": ("s390", "s390x")}
+
+def isLittleEndian(cpu):
+ if cpus[cpu][ENDIAN] == "little":
+ return True
+ return ""
+
+def is64bit(cpu):
+ # Only use this one for files with CPUS in their paths
+ if cpus[cpu][BITS] == 64:
+ return True
+ return ""
+
+def isRegisterWindow(cpu):
+ if cpus[cpu][RWINDOW]:
+ return True
+ return ""
+
+def preprocess(src, cpu):
+ other_cpus = [key.upper() for key in modes.keys() if key != cpu]
+ cpu = cpu.upper()
+ things = re.compile(r"(.*?)(/\*|//|^[ \t]*#)(.*)", re.S | re.M)
+ ends = {"/*": "*/"}
+ COPY, COND_TRUE, COND_FALSE = 1, 2, 3
+ mode = [COPY]
+ dst = ""
+ while src:
+ thing = things.match(src)
+ if not thing:
+ if mode[-1] != COND_FALSE:
+ dst += src
+ break
+ before, thing, src = thing.groups()
+ src = thing + src
+ if mode[-1] != COND_FALSE:
+ dst += before
+ end = ends.get(thing, "\n")
+ index = src.find(end)
+ assert index >= 0
+ index += len(end)
+ thing = src[:index]
+ src = src[index:]
+ if not thing.startswith("#"):
+ if mode[-1] != COND_FALSE:
+ dst += thing
+ continue
+ args = thing.strip().split()
+ cmd = args.pop(0)
+ if cmd == "#":
+ cmd += args.pop(0)
+
+ if cmd in ("#include", "#define", "#undef"):
+ if mode[-1] != COND_FALSE:
+ dst += thing
+ elif cmd in ("#ifdef", "#ifndef"):
+ us, them = {
+ "#ifdef": (COND_TRUE, COND_FALSE),
+ "#ifndef": (COND_FALSE, COND_TRUE)}[cmd]
+ [what] = args
+ if what == cpu:
+ mode.append(us)
+ elif what in other_cpus:
+ mode.append(them)
+ else:
+ mode.append(COPY)
+ dst += thing
+ elif cmd == "#if":
+ for check in [cpu] + other_cpus:
+ assert "defined(%s)" % check not in args
+ mode.append(COPY)
+ dst += thing
+ elif cmd == "#else":
+ if mode[-1] == COND_TRUE:
+ mode[-1] = COND_FALSE
+ elif mode[-1] == COND_FALSE:
+ mode[-1] = COND_TRUE
+ else:
+ dst += thing
+ elif cmd == "#endif":
+ if mode[-1] == COPY:
+ dst += thing
+ mode.pop()
+ else:
+ assert False
+
+ assert mode == [COPY]
+ return dst.replace("_LP64", "PPC64")
+
+def untabify(line):
+ bits = line.split("\t")
+ line = bits.pop(0)
+ for bit in bits:
+ line += " " * (8 - len(line) % 8)
+ line += bit
+ return line
+
+def template(src, dst, basecpu, cpu):
+ bits = open(src, "r").read().split("@@")
+ assert len(bits) & 1
+ for i in xrange(1, len(bits), 2):
+ result = eval(bits[i].strip())
+ if not result:
+ result = ""
+ bits[i] = result
+ result = "".join(bits)
+ if src.split(".")[-1] in ("c", "h", "cpp", "hpp"):
+ result = preprocess(result, cpu)
+ if src.split(".")[-1] != "c":
+ result = "\n".join(
+ [untabify(line.rstrip()) for line in result.split("\n")])
+ if os.path.exists(dst):
+ existing = open(dst, "r").read()
+ if result == existing:
+ return
+ trim = os.getcwd() + os.sep
+ assert dst.startswith(trim)
+ print "creating", dst[len(trim):]
+ dir = os.path.dirname(dst)
+ if not os.path.isdir(dir):
+ os.makedirs(dir)
+ open(dst, "w").write(result)
+
+def skip(item):
+ prefixes, suffixes = ["."], ["~", ".orig", ".rej"]
+ for prefix in prefixes:
+ if item.startswith(prefix):
+ return True
+ for suffix in suffixes:
+ if item.endswith(suffix):
+ return True
+ return False
+
+def visit((srcdir, dstdir, cpus), dir, items):
+ if ".hg" in items:
+ items.remove(".hg")
+ for item in items:
+ if skip(item):
+ continue
+ path = os.path.join(dir, item)
+ if not os.path.isfile(path):
+ continue
+ if path.find("CPU") == -1:
+ continue
+ multi = path.find("CPUS") >= 0
+ trim = srcdir + os.sep
+ assert path.startswith(trim)
+ trim = len(trim)
+ for basecpu in cpus:
+ for cpu in modes[basecpu]:
+ template(
+ path, os.path.join(dstdir,path[trim:] \
+ .replace("CPUS", cpu) \
+ .replace("CPU", basecpu)),
+ basecpu, cpu)
+ if not multi:
+ break
+
+if __name__ == "__main__":
+ import sys
+ srcdir = os.path.dirname(os.path.abspath(sys.argv[0]))
+ dstdir = os.path.join(os.getcwd(), "ports")
+ if not os.path.isdir(dstdir):
+ print >>sys.stderr, "run me within the IcedTea toplevel directory"
+ sys.exit(1)
+ if len(sys.argv) < 2:
+ cpus = modes.keys()
+ cpus.sort()
+ cpus = "|".join(cpus)
+ print >>sys.stderr, "usage: %s %s..." % (sys.argv[0], cpus)
+ sys.exit(1)
+ os.path.walk(srcdir, visit, (srcdir, dstdir, sys.argv[1:]))
diff -r 53c81bc2c2cf -r 1f7f39188e9f contrib/templater/hotspot/build/linux/makefiles/CPUS.make
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/contrib/templater/hotspot/build/linux/makefiles/CPUS.make Fri Nov 16 13:18:29 2007 +0000
@@ -0,0 +1,46 @@
+#
+# Copyright 2003-2005 Sun Microsystems, Inc. All Rights Reserved.
+# Copyright 2007 Red Hat, Inc.
+# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+#
+# This code is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License version 2 only, as
+# published by the Free Software Foundation.
+#
+# This code is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+# version 2 for more details (a copy is included in the LICENSE file that
+# accompanied this code).
+#
+# You should have received a copy of the GNU General Public License version
+# 2 along with this work; if not, write to the Free Software Foundation,
+# Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+#
+# Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+# CA 95054 USA or visit www.sun.com if you need additional information or
+# have any questions.
+#
+#
+
+# Not included in includeDB because it has no dependencies
+Obj_Files += linux_@@cpu@@.o
+
+# The copied fdlibm routines in sharedRuntimeTrig.o must not be optimized
+OPT_CFLAGS/sharedRuntimeTrig.o = $(OPT_CFLAGS/NOOPT)
+# The copied fdlibm routines in sharedRuntimeTrans.o must not be optimized
+OPT_CFLAGS/sharedRuntimeTrans.o = $(OPT_CFLAGS/NOOPT)
+@@
+
+isLittleEndian(cpu) and """
+# Specify that the CPU is little endian
+CFLAGS += -DVM_LITTLE_ENDIAN
+"""
+@@@@
+
+is64bit(cpu) and """
+# Specify that the CPU is 64 bit
+CFLAGS += -D_LP64=1
+"""
+@@
+OPT_CFLAGS/compactingPermGenGen.o = -O1
diff -r 53c81bc2c2cf -r 1f7f39188e9f contrib/templater/hotspot/build/linux/platform_CPUS
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/contrib/templater/hotspot/build/linux/platform_CPUS Fri Nov 16 13:18:29 2007 +0000
@@ -0,0 +1,19 @@
+os_family = linux
+
+arch = @@basecpu@@
+
+arch_model = @@basecpu@@
+
+os_arch = linux_@@basecpu@@
+
+os_arch_model = linux_@@basecpu@@
+
+lib_arch = @@basecpu@@
+
+compiler = gcc
+
+gnu_dis_arch = @@basecpu@@
+
+sysdefs = -DLINUX -D_GNU_SOURCE -D@@basecpu.upper()@@@@
+basecpu == "ppc" and (" -D" + (cpu == "ppc" and "PPC32" or "PPC64"))
+@@ -DCC_INTERP -DXXX_EVIL_EVIL_EVIL
diff -r 53c81bc2c2cf -r 1f7f39188e9f contrib/templater/hotspot/src/cpu/CPU/vm/assembler_CPU.cpp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/contrib/templater/hotspot/src/cpu/CPU/vm/assembler_CPU.cpp Fri Nov 16 13:18:29 2007 +0000
@@ -0,0 +1,1375 @@
+/*
+ * Copyright 2003-2007 Sun Microsystems, Inc. All Rights Reserved.
+ * Copyright 2007 Red Hat, Inc.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
+ * CA 95054 USA or visit www.sun.com if you need additional information or
+ * have any questions.
+ *
+ */
+
+#include "incls/_precompiled.incl"
+#include "incls/_assembler_@@cpu@@.cpp.incl"
+
+#ifdef PPC
+
+// Fill empty space with zeros.
+// (0x00000000 is an illegal instruction on ppc)
+
+int AbstractAssembler::code_fill_byte()
+{
+ return 0x00;
+}
+
+// Instruction emitters for the various forms.
+// Every instruction should ultimately come through one of these.
+
+void Assembler::emit_instruction(int opcode, int li, bool aa, bool lk)
+{
+ // I-form
+ assert(!(opcode & ~0x3f), "invalid opcode");
+ assert(!(li & ~0xffffff), "invalid operand");
+ emit_long(opcode << 26 | li << 2 | aa << 1 | lk);
+}
+void Assembler::emit_instruction(int opcode, int bo, int bi, int bd,
+ bool aa, bool lk) {
+ // B-form (includes SC-form)
+ assert(!(opcode & ~0x3f), "invalid opcode");
+ assert(!(bo & ~0x1f), "invalid operand");
+ assert(!(bi & ~0x1f), "invalid operand");
+ assert(!(bd & ~0x3fff), "invalid operand");
+ emit_long(opcode << 26 | bo << 21 | bi << 16 | bd << 2 | aa << 1 | lk);
+}
+void Assembler::emit_instruction(int opcode, int a, int b, int c)
+{
+ // D-form
+ assert(!(opcode & ~0x3f), "invalid opcode");
+ assert(!(a & ~0x1f), "invalid operand");
+ assert(!(b & ~0x1f), "invalid operand");
+ if (c < 0) {
+ assert((c & ~0xffff) == ~0xffff, "invalid operand");
+ c &= 0xffff;
+ }
+ else
+ assert(!(c & ~0xffff), "invalid operand");
+ emit_long(opcode << 26 | a << 21 | b << 16 | c);
+}
+void Assembler::emit_instruction(int opcode, int a, int b, int c, int d)
+{
+ // DS-form
+ assert(!(opcode & ~0x3f), "invalid opcode");
+ assert(!(a & ~0x1f), "invalid operand");
+ assert(!(b & ~0x1f), "invalid operand");
+ if (c < 0) {
+ assert((c & ~0x3fff) == ~0x3fff, "invalid operand");
+ c &= 0x3fff;
+ }
+ else
+ assert(!(c & ~0x3fff), "invalid operand");
+ assert(!(d & ~0x3), "invalid operand");
+ emit_long(opcode << 26 | a << 21 | b << 16 | c << 2 | d);
+}
+void Assembler::emit_instruction(int opcode, int a, int b, int c, int xo,
+ bool rc) {
+ // X-form
+ assert(!(opcode & ~0x3f), "invalid opcode");
+ assert(!(a & ~0x1f), "invalid operand");
+ assert(!(b & ~0x1f), "invalid operand");
+ assert(!(c & ~0x1f), "invalid operand");
+ assert(!(xo & ~0x3ff), "invalid operand");
+ emit_long(opcode << 26 | a << 21 | b << 16 | c << 11 | xo << 1 | rc);
+}
+void Assembler::emit_instruction(int opcode, int a, int b, int c, int d,
+ int e, bool rc) {
+ switch (opcode) {
+ case 21:
+ // M-form
+ assert(!(a & ~0x1f), "invalid operand");
+ assert(!(b & ~0x1f), "invalid operand");
+ assert(!(c & ~0x1f), "invalid operand");
+ assert(!(d & ~0x1f), "invalid operand");
+ assert(!(e & ~0x1f), "invalid operand");
+ break;
+
+ case 30:
+ // MD-form
+ assert(!(a & ~0x1f), "invalid operand");
+ assert(!(b & ~0x1f), "invalid operand");
+ assert(!(c & ~0x3f), "invalid operand");
+ assert(!(d & ~0x3f), "invalid operand");
+ assert(!(e & ~0x07), "invalid operand");
+ {
+ int C = c & 0x1f;
+ int D = d & 0x1f;
+ int E = (d & 0x20) >> 1 | e << 1 | (c & 0x20) >> 5;
+
+ c = C; d = D; e = E;
+ }
+ break;
+
+ default:
+ ShouldNotReachHere();
+ }
+ emit_long(opcode << 26 | a << 21 | b << 16 | c << 11 | d << 6 | e << 1 | rc);
+}
+
+// Wrappers for the instruction emitters.
+// These handle casting and stuff.
+
+void Assembler::emit_instruction(int opcode, Register a, Register b, int c)
+{
+ emit_instruction(opcode, a->encoding(), b->encoding(), c);
+}
+void Assembler::emit_instruction(int opcode, Register a, Register b, int c,
+ int d) {
+ emit_instruction(opcode, a->encoding(), b->encoding(), c, d);
+}
+void Assembler::emit_instruction(int opcode, FloatRegister a, Register b,
+ int c) {
+ emit_instruction(opcode, a->encoding(), b->encoding(), c);
+}
+void Assembler::emit_instruction(int opcode, Register a, const Address& b)
+{
+ emit_instruction(opcode, a, b.base(), b.displacement());
+}
+void Assembler::emit_instruction(int opcode, Register a, const Address& b,
+ int c) {
+ emit_instruction(opcode, a, b.base(), b.displacement() >> 2, c);
+}
+void Assembler::emit_instruction(int opcode, FloatRegister a, const Address& b)
+{
+ emit_instruction(opcode, a, b.base(), b.displacement());
+}
+void Assembler::emit_instruction(int opcode, Register a, int b, int c,
+ int xo, bool rc) {
+ emit_instruction(opcode, a->encoding(), b, c, xo, rc);
+}
+void Assembler::emit_instruction(int opcode, Register a, Register b,
+ Register c, int xo, bool rc) {
+ emit_instruction(opcode, a->encoding(), b->encoding(), c->encoding(),
+ xo, rc);
+}
+void Assembler::emit_instruction(int opcode, Register a,
+ SpecialPurposeRegister b, int c, int xo,
+ bool rc) {
+ emit_instruction(opcode, a->encoding(), b->encoding(), c, xo, rc);
+}
+void Assembler::emit_instruction(int opcode, SpecialPurposeRegister a,
+ Register b, int c, int xo, bool rc) {
+ emit_instruction(opcode, a->encoding(), b->encoding(), c, xo, rc);
+}
+void Assembler::emit_instruction(int opcode, Register a, Register b,
+ int c, int d, int e, bool rc) {
+ emit_instruction(opcode, a->encoding(), b->encoding(), c, d, e, rc);
+}
+void Assembler::emit_instruction(int opcode, int a, Register b, Register c,
+ int d, bool rc) {
+ emit_instruction(opcode, a, b->encoding(), c->encoding(), d, rc);
+}
+void Assembler::emit_instruction(int opcode, ConditionRegister a, bool l,
+ Register b, Register c, int d, bool rc) {
+ emit_instruction(opcode, a->encoding() << 2 | l, b, c, d, rc);
+}
+void Assembler::emit_instruction(int opcode, ConditionRegister a, bool l,
+ Register b, int c) {
+ emit_instruction(opcode, a->encoding() << 2 | l, b->encoding(), c);
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