/hg/openjdk6-mips: 4 new changesets
liuqi at icedtea.classpath.org
liuqi at icedtea.classpath.org
Wed Dec 1 23:12:17 PST 2010
changeset 75473a9073f5 in /hg/openjdk6-mips
details: http://icedtea.classpath.org/hg/openjdk6-mips?cmd=changeset;node=75473a9073f5
author: Ao Qi <aoqi at loongson.cn>
date: Wed Dec 01 17:12:39 2010 +0800
Fix bugs occurred when adding -XX:+VerifyOops.
Array length should not be stored in a register of oop type.
changeset dd1d79f9798b in /hg/openjdk6-mips
details: http://icedtea.classpath.org/hg/openjdk6-mips?cmd=changeset;node=dd1d79f9798b
author: Ao Qi <aoqi at loongson.cn>
date: Wed Dec 01 17:39:16 2010 +0800
Fix deoptimization bugs.
Fix bugs of exception_offset and reexecute_offset entries, and of
saving return value into registers.
changeset 18922e417eb4 in /hg/openjdk6-mips
details: http://icedtea.classpath.org/hg/openjdk6-mips?cmd=changeset;node=18922e417eb4
author: Ao Qi <aoqi at loongson.cn>
date: Wed Dec 01 17:47:08 2010 +0800
Fix bugs in reg2mem and mem2reg of T_LONG & needs_patching cases.
changeset 15f398a44411 in /hg/openjdk6-mips
details: http://icedtea.classpath.org/hg/openjdk6-mips?cmd=changeset;node=15f398a44411
author: Ao Qi <aoqi at loongson.cn>
date: Wed Dec 01 17:08:35 2010 +0800
Fix verify_oop bug.
When verify oop in A0, A0 would be coverd by b.
diffstat:
4 files changed, 361 insertions(+), 368 deletions(-)
hotspot/src/cpu/mips/vm/assembler_mips.cpp | 2
hotspot/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp | 675 +++++++++++-----------
hotspot/src/cpu/mips/vm/c1_LIRGenerator_mips.cpp | 4
hotspot/src/cpu/mips/vm/sharedRuntime_mips.cpp | 48 -
diffs (truncated from 897 to 500 lines):
diff -r 9fdc8715b0a2 -r 15f398a44411 hotspot/src/cpu/mips/vm/assembler_mips.cpp
--- a/hotspot/src/cpu/mips/vm/assembler_mips.cpp Fri Nov 26 12:00:58 2010 +0800
+++ b/hotspot/src/cpu/mips/vm/assembler_mips.cpp Wed Dec 01 17:08:35 2010 +0800
@@ -2069,8 +2069,8 @@ void MacroAssembler::verify_oop(Register
sw(AT, SP ,- 6*wordSize);
sw(T9, SP ,- 7*wordSize);
addiu(SP, SP, - 7 * wordSize);
+ move(A1, reg);
move(A0, (int)b);
- move(A1, reg);
// call indirectly to solve generation ordering problem
move(AT, (int)StubRoutines::verify_oop_subroutine_entry_address());
lw(T9, AT, 0);
diff -r 9fdc8715b0a2 -r 15f398a44411 hotspot/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp
--- a/hotspot/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp Fri Nov 26 12:00:58 2010 +0800
+++ b/hotspot/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp Wed Dec 01 17:08:35 2010 +0800
@@ -432,7 +432,7 @@ void LIR_Assembler::emit_deopt_handler()
#endif // ASSERT
compilation()->offsets()->set_value(CodeOffsets::Deopt, code_offset());
-
+
__ call(SharedRuntime::deopt_blob()->unpack());
__ delayed()->nop();
@@ -811,156 +811,155 @@ void LIR_Assembler::reg2mem(LIR_Opr src,
void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info,bool pop_fpu_stack, bool/*unaliged*/) {
LIR_Address* to_addr = dest->as_address_ptr();
Register dest_reg = to_addr->base()->as_register();
- PatchingStub* patch = NULL;
- bool needs_patching = (patch_code != lir_patch_none);
+ PatchingStub* patch = NULL;
+ bool needs_patching = (patch_code != lir_patch_none);
Register disp_reg = NOREG;
- int disp_value = to_addr->disp();
-
- if (type == T_ARRAY || type == T_OBJECT) {
+ int disp_value = to_addr->disp();
+
+ if (type == T_ARRAY || type == T_OBJECT) {
__ verify_oop(src->as_register());
}
- if (needs_patching) {
- patch = new PatchingStub(_masm, PatchingStub::access_field_id);
- assert(!src->is_double_cpu() ||
- patch_code == lir_patch_none ||
- patch_code == lir_patch_normal,
- "patching doesn't match register");
- }
-
- if (info != NULL) {
- add_debug_info_for_null_check_here(info);
- }
- if (needs_patching) {
- disp_reg = AT;
- __ lui(AT, Assembler::split_high(disp_value));
- __ addiu(AT, AT, Assembler::split_low(disp_value));
- } else if (!Assembler::is_simm16(disp_value)) {
- disp_reg = AT;
- __ lui(AT, Assembler::split_high(disp_value));
- }
- int offset = code_offset();
-
- switch(type) {
- case T_DOUBLE:
- assert(src->is_double_fpu(), "just check");
- if (disp_reg == noreg) {
- __ swc1(src->as_double_reg(), dest_reg, disp_value);
- __ swc1(src->as_double_reg()+1, dest_reg, disp_value+4);
- } else if (needs_patching) {
- __ add(AT, dest_reg, disp_reg);
- offset = code_offset();
- __ swc1(src->as_double_reg(), AT, 0);
- __ swc1(src->as_double_reg()+1, AT, 4);
- } else {
- __ add(AT, dest_reg, disp_reg);
- offset = code_offset();
- __ swc1(src->as_double_reg(), AT, Assembler::split_low(disp_value));
- __ swc1(src->as_double_reg()+1, AT, Assembler::split_low(disp_value) + 4);
- }
- break;
-
- case T_FLOAT:
- // assert(src->is_single_cpu(), "just check");
-
- if (disp_reg == noreg) {
- __ swc1(src->as_float_reg(), dest_reg, disp_value);
- } else if(needs_patching) {
- __ add(AT, dest_reg, disp_reg);
- offset = code_offset();
- __ swc1(src->as_float_reg(), AT, 0);
- } else {
- __ add(AT, dest_reg, disp_reg);
- offset = code_offset();
- __ swc1(src->as_float_reg(), AT, Assembler::split_low(disp_value));
- }
- break;
-
- case T_LONG: {
- Register from_lo = src->as_register_lo();
- Register from_hi = src->as_register_hi();
- Register base = to_addr->base()->as_register();
- Register index = noreg;
- if (to_addr->index()->is_register()) {
- index = to_addr->index()->as_register();
- }
- if (base == from_lo || index == from_lo) {
- assert(base != from_hi, "can't be");
- assert(index == noreg || (index != base && index != from_hi), "can't handle this");
- __ sw(from_hi,as_Address_hi(to_addr));
- if (patch != NULL) {
- patching_epilog(patch, lir_patch_high, base, info);
- patch = new PatchingStub(_masm, PatchingStub::access_field_id);
- patch_code = lir_patch_low;
- }
- __ sw(from_lo,as_Address_lo(to_addr));
- } else {
- assert(index == noreg || (index != base && index != from_lo), "can't handle this");
- __ sw(from_lo,as_Address_lo(to_addr));
- if (patch != NULL) {
- patching_epilog(patch, lir_patch_low, base, info);
- patch = new PatchingStub(_masm, PatchingStub::access_field_id);
- patch_code = lir_patch_high;
- }
- __ sw(from_hi,as_Address_hi(to_addr));
- }
- break;
- }
- case T_ADDRESS:
- case T_ARRAY:
- case T_OBJECT:
- case T_INT:
- //assert(from_reg.is_word(), "just check");
- if (disp_reg == noreg) {
- __ sw(src->as_register(), dest_reg, disp_value);
- } else if (needs_patching) {
- __ add(AT, dest_reg, disp_reg);
- offset = code_offset();
- __ sw(src->as_register(), AT, 0);
- } else {
- __ add(AT, dest_reg, disp_reg);
- offset = code_offset();
- __ sw(src->as_register(), AT, Assembler::split_low(disp_value));
- }
- break;
-
- case T_CHAR:
- case T_SHORT:
-// assert(from_reg.is_word(), "just check");
-
- if (disp_reg == noreg) {
- __ sh(src->as_register(), dest_reg, disp_value);
- } else if (needs_patching) {
- __ add(AT, dest_reg, disp_reg);
- offset = code_offset();
- __ sh(src->as_register(), AT, 0);
- } else {
- __ add(AT, dest_reg, disp_reg);
- offset = code_offset();
- __ sh(src->as_register(), AT, Assembler::split_low(disp_value));
- }
- break;
-
- case T_BYTE:
- case T_BOOLEAN:
- assert(src->is_single_cpu(), "just check");
-
- if (disp_reg == noreg) {
- __ sb(src->as_register(), dest_reg, disp_value);
- } else if (needs_patching) {
- __ add(AT, dest_reg, disp_reg);
- offset = code_offset();
- __ sb(src->as_register(), AT, 0);
- } else {
- __ add(AT, dest_reg, disp_reg);
- offset = code_offset();
- __ sb(src->as_register(), AT, Assembler::split_low(disp_value));
- }
- break;
-
- default:
- ShouldNotReachHere();
- }
+ if (needs_patching) {
+ patch = new PatchingStub(_masm, PatchingStub::access_field_id);
+ assert(!src->is_double_cpu() ||
+ patch_code == lir_patch_none ||
+ patch_code == lir_patch_normal,
+ "patching doesn't match register");
+ }
+
+ if (info != NULL) {
+ add_debug_info_for_null_check_here(info);
+ }
+ if (needs_patching) {
+ disp_reg = AT;
+ __ lui(AT, Assembler::split_high(disp_value));
+ __ addiu(AT, AT, Assembler::split_low(disp_value));
+ } else if (!Assembler::is_simm16(disp_value)) {
+ disp_reg = AT;
+ __ lui(AT, Assembler::split_high(disp_value));
+ }
+ int offset = code_offset();
+
+ switch(type) {
+ case T_DOUBLE:
+ assert(src->is_double_fpu(), "just check");
+ if (disp_reg == noreg) {
+ __ swc1(src->as_double_reg(), dest_reg, disp_value);
+ __ swc1(src->as_double_reg()+1, dest_reg, disp_value+4);
+ } else if (needs_patching) {
+ __ add(AT, dest_reg, disp_reg);
+ offset = code_offset();
+ __ swc1(src->as_double_reg(), AT, 0);
+ __ swc1(src->as_double_reg()+1, AT, 4);
+ } else {
+ __ add(AT, dest_reg, disp_reg);
+ offset = code_offset();
+ __ swc1(src->as_double_reg(), AT, Assembler::split_low(disp_value));
+ __ swc1(src->as_double_reg()+1, AT, Assembler::split_low(disp_value) + 4);
+ }
+ break;
+
+ case T_FLOAT:
+ if (disp_reg == noreg) {
+ __ swc1(src->as_float_reg(), dest_reg, disp_value);
+ } else if(needs_patching) {
+ __ add(AT, dest_reg, disp_reg);
+ offset = code_offset();
+ __ swc1(src->as_float_reg(), AT, 0);
+ } else {
+ __ add(AT, dest_reg, disp_reg);
+ offset = code_offset();
+ __ swc1(src->as_float_reg(), AT, Assembler::split_low(disp_value));
+ }
+ break;
+
+ case T_LONG: {
+ Register from_lo = src->as_register_lo();
+ Register from_hi = src->as_register_hi();
+ Register base = to_addr->base()->as_register();
+ Register index = noreg;
+ if (to_addr->index()->is_register()) {
+ index = to_addr->index()->as_register();
+ }
+ if (base == from_lo || index == from_lo) {
+ assert(base != from_hi, "can't be");
+ assert(index == noreg || (index != base && index != from_hi), "can't handle this");
+ if (needs_patching) {
+ __ add(AT, dest_reg, disp_reg);
+ offset = code_offset();
+ __ sw(from_hi,AT, longSize/2);
+ __ sw(from_lo, AT, 0);
+ } else {
+ __ sw(from_hi,as_Address_hi(to_addr));
+ __ sw(from_lo,as_Address_lo(to_addr));
+ }
+ } else {
+ assert(index == noreg || (index != base && index != from_lo), "can't handle this");
+ if (needs_patching) {
+ __ add(AT, dest_reg, disp_reg);
+ offset = code_offset();
+ __ sw(from_lo,AT, 0);
+ __ sw(from_hi, AT, longSize/2);
+ } else {
+ __ sw(from_lo,as_Address_lo(to_addr));
+ __ sw(from_hi,as_Address_hi(to_addr));
+ }
+ }
+ break;
+ }
+ case T_ADDRESS:
+ case T_ARRAY:
+ case T_OBJECT:
+ case T_INT:
+ if (disp_reg == noreg) {
+ __ sw(src->as_register(), dest_reg, disp_value);
+ } else if (needs_patching) {
+ __ add(AT, dest_reg, disp_reg);
+ offset = code_offset();
+ __ sw(src->as_register(), AT, 0);
+ } else {
+ __ add(AT, dest_reg, disp_reg);
+ offset = code_offset();
+ __ sw(src->as_register(), AT, Assembler::split_low(disp_value));
+ }
+ break;
+
+ case T_CHAR:
+ case T_SHORT:
+ if (disp_reg == noreg) {
+ __ sh(src->as_register(), dest_reg, disp_value);
+ } else if (needs_patching) {
+ __ add(AT, dest_reg, disp_reg);
+ offset = code_offset();
+ __ sh(src->as_register(), AT, 0);
+ } else {
+ __ add(AT, dest_reg, disp_reg);
+ offset = code_offset();
+ __ sh(src->as_register(), AT, Assembler::split_low(disp_value));
+ }
+ break;
+
+ case T_BYTE:
+ case T_BOOLEAN:
+ assert(src->is_single_cpu(), "just check");
+
+ if (disp_reg == noreg) {
+ __ sb(src->as_register(), dest_reg, disp_value);
+ } else if (needs_patching) {
+ __ add(AT, dest_reg, disp_reg);
+ offset = code_offset();
+ __ sb(src->as_register(), AT, 0);
+ } else {
+ __ add(AT, dest_reg, disp_reg);
+ offset = code_offset();
+ __ sb(src->as_register(), AT, Assembler::split_low(disp_value));
+ }
+ break;
+
+ default:
+ ShouldNotReachHere();
+ }
if (needs_patching) {
patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
@@ -970,32 +969,32 @@ void LIR_Assembler::reg2mem(LIR_Opr src,
void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
- assert(src->is_stack(), "should not call otherwise");
+ assert(src->is_stack(), "should not call otherwise");
assert(dest->is_register(), "should not call otherwise");
- if (dest->is_single_cpu()) {
+ if (dest->is_single_cpu()) {
__ lw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
if (type == T_ARRAY || type == T_OBJECT) {
__ verify_oop(dest->as_register());
}
- } else if (dest->is_double_cpu()) {
- Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(),lo_word_offset_in_bytes);
- Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
- __ lw(dest->as_register_lo(), src_addr_LO);
- __ lw(dest->as_register_hi(), src_addr_HI);
- }else if (dest->is_single_fpu()) {
- Address addr = frame_map()->address_for_slot(src->single_stack_ix());
- __ lwc1(dest->as_float_reg(), addr);
- } else if (dest->is_double_fpu()) {
- Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(),lo_word_offset_in_bytes);
- Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
- __ lwc1(dest->as_double_reg(), src_addr_LO);
- __ lwc1(dest->as_double_reg()+1, src_addr_HI);
- } else {
- assert(dest->is_single_cpu(), "cannot be anything else but a single cpu");
- assert(type!= T_ILLEGAL, "Bad type in stack2reg")
- Address addr = frame_map()->address_for_slot(src->single_stack_ix());
- __ lw(dest->as_register(), addr);
- }
+ } else if (dest->is_double_cpu()) {
+ Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(),lo_word_offset_in_bytes);
+ Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
+ __ lw(dest->as_register_lo(), src_addr_LO);
+ __ lw(dest->as_register_hi(), src_addr_HI);
+ }else if (dest->is_single_fpu()) {
+ Address addr = frame_map()->address_for_slot(src->single_stack_ix());
+ __ lwc1(dest->as_float_reg(), addr);
+ } else if (dest->is_double_fpu()) {
+ Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(),lo_word_offset_in_bytes);
+ Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
+ __ lwc1(dest->as_double_reg(), src_addr_LO);
+ __ lwc1(dest->as_double_reg()+1, src_addr_HI);
+ } else {
+ assert(dest->is_single_cpu(), "cannot be anything else but a single cpu");
+ assert(type!= T_ILLEGAL, "Bad type in stack2reg")
+ Address addr = frame_map()->address_for_slot(src->single_stack_ix());
+ __ lw(dest->as_register(), addr);
+ }
}
void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
@@ -1016,189 +1015,193 @@ void LIR_Assembler::stack2stack(LIR_Opr
// if patching needed, be sure the instruction at offset is a MoveMemReg
void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool) {
- assert(src->is_address(), "should not call otherwise");
+ assert(src->is_address(), "should not call otherwise");
assert(dest->is_register(), "should not call otherwise");
LIR_Address* addr = src->as_address_ptr();
Address from_addr = as_Address(addr);
-
- Register src_reg = addr->base()->as_register();
- Register disp_reg = noreg;
- int disp_value = addr->disp();
- bool needs_patching = (patch_code != lir_patch_none);
-
- PatchingStub* patch = NULL;
- if (needs_patching) {
- patch = new PatchingStub(_masm, PatchingStub::access_field_id);
-// assert(!to_reg.is_long() || patch_code == LIR_Op1::patch_low || patch_code == LIR_Op1::patch_high, "patching doesn't match register");
- }
-
- // we must use lui&addiu,
- if (needs_patching) {
- disp_reg = AT;
- __ lui(AT, Assembler::split_high(disp_value));
- __ addiu(AT, AT, Assembler::split_low(disp_value));
- } else if (!Assembler::is_simm16(disp_value)) {
- disp_reg = AT;
- __ lui(AT, Assembler::split_high(disp_value));
- }
-
- // remember the offset of the load. The patching_epilog must be done
- // before the call to add_debug_info, otherwise the PcDescs don't get
- // entered in increasing order.
- int offset = code_offset();
-
- switch(type) {
+
+ Register src_reg = addr->base()->as_register();
+ Register disp_reg = noreg;
+ int disp_value = addr->disp();
+ bool needs_patching = (patch_code != lir_patch_none);
+
+ PatchingStub* patch = NULL;
+ if (needs_patching) {
+ patch = new PatchingStub(_masm, PatchingStub::access_field_id);
+ }
+
+ // we must use lui&addiu,
+ if (needs_patching) {
+ disp_reg = AT;
+ __ lui(AT, Assembler::split_high(disp_value));
+ __ addiu(AT, AT, Assembler::split_low(disp_value));
+ } else if (!Assembler::is_simm16(disp_value)) {
+ disp_reg = AT;
+ __ lui(AT, Assembler::split_high(disp_value));
+ }
+
+ // remember the offset of the load. The patching_epilog must be done
+ // before the call to add_debug_info, otherwise the PcDescs don't get
+ // entered in increasing order.
+ int offset = code_offset();
+
+ switch(type) {
case T_BOOLEAN:
case T_BYTE: {
- //assert(to_reg.is_word(), "just check");
- if (disp_reg == noreg) {
- __ lb(dest->as_register(), src_reg, disp_value);
- } else if (needs_patching) {
- __ add(AT, src_reg, disp_reg);
- offset = code_offset();
- __ lb(dest->as_register(), AT, 0);
- } else {
- __ add(AT, src_reg, disp_reg);
- offset = code_offset();
- __ lb(dest->as_register(), AT, Assembler::split_low(disp_value));
- }
- }
- break;
-
+ //assert(to_reg.is_word(), "just check");
+ if (disp_reg == noreg) {
+ __ lb(dest->as_register(), src_reg, disp_value);
+ } else if (needs_patching) {
+ __ add(AT, src_reg, disp_reg);
+ offset = code_offset();
+ __ lb(dest->as_register(), AT, 0);
+ } else {
+ __ add(AT, src_reg, disp_reg);
+ offset = code_offset();
+ __ lb(dest->as_register(), AT, Assembler::split_low(disp_value));
+ }
+ }
+ break;
+
case T_CHAR: {
- //assert(to_reg.is_word(), "just check");
- if (disp_reg == noreg) {
- __ lhu(dest->as_register(), src_reg, disp_value);
- } else if (needs_patching) {
- __ add(AT, src_reg, disp_reg);
- offset = code_offset();
- __ lhu(dest->as_register(), AT, 0);
- } else {
- __ add(AT, src_reg, disp_reg);
- offset = code_offset();
- __ lhu(dest->as_register(), AT, Assembler::split_low(disp_value));
- }
- }
- break;
-
+ //assert(to_reg.is_word(), "just check");
+ if (disp_reg == noreg) {
+ __ lhu(dest->as_register(), src_reg, disp_value);
+ } else if (needs_patching) {
+ __ add(AT, src_reg, disp_reg);
+ offset = code_offset();
+ __ lhu(dest->as_register(), AT, 0);
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