[Bug 434] New: Shark on ARM SIGSEGV from null pointer in $r2 instead of %stack_pointer_addr
bugzilla-daemon at icedtea.classpath.org
bugzilla-daemon at icedtea.classpath.org
Fri Jan 22 08:07:18 PST 2010
http://icedtea.classpath.org/bugzilla/show_bug.cgi?id=434
Summary: Shark on ARM SIGSEGV from null pointer in $r2 instead of
%stack_pointer_addr
Product: IcedTea
Version: 6-hg
Platform: Other
OS/Version: Linux
Status: NEW
Severity: normal
Priority: P2
Component: Shark
AssignedTo: unassigned at icedtea.classpath.org
ReportedBy: xerxes at zafena.se
testcase run CaffeineMarkEmbeddedApp from cm30, this have worked flawlessly
before using shark on arm so i suspect a regression using the latest shark.
Starting program:
/media/disk/icedtea6-tot/openjdk-ecj/build/linux-arm/j2sdk-image/bin/java
CaffeineMarkEmbeddedApp
[Thread debugging using libthread_db enabled]
[New Thread 0x40020670 (LWP 17688)]
[New Thread 0x40d24490 (LWP 17765)]
[New Thread 0x672f2490 (LWP 17766)]
[New Thread 0x673f2490 (LWP 17792)]
[New Thread 0x674f2490 (LWP 17793)]
[New Thread 0x67631490 (LWP 17859)]
[New Thread 0x67751490 (LWP 17860)]
[New Thread 0x67851490 (LWP 17861)]
[New Thread 0x678d1490 (LWP 17862)]
Program received signal SIGSEGV, Segmentation fault.
[Switching to Thread 0x40d24490 (LWP 17765)]
0x676536e4 in ?? ()
(gdb) disassemble $pc-4 $pc+256
Dump of assembler code from 0x676536e0 to 0x676537e4:
0x676536e0: push {r4, r5, r6, r7, r11, lr}
0x676536e4: ldr r12, [r2, #480]
0x676536e8: ldr r3, [r2, #472]
0x676536ec: sub r4, r12, #40 ; 0x28
0x676536f0: cmp r4, r3
0x676536f4: bcc 0x6765384c
0x676536f8: mov r5, r2
0x676536fc: str r4, [r4, #24]
0x67653700: mov r2, #3 ; 0x3
0x67653704: str r2, [r4, #32]
0x67653708: ldr r2, [r5, #484]
0x6765370c: str r2, [r4, #36]
0x67653710: add r2, r4, #36 ; 0x24
0x67653714: str r2, [r5, #484]
0x67653718: ldr r6, [r4, #40]
0x6765371c: ldr r2, [r4, #44]
0x67653720: cmp r6, #0 ; 0x0
0x67653724: beq 0x676537b4
0x67653728: ldr r3, [r1, #16]
0x6765372c: add r7, r4, #4 ; 0x4
0x67653730: add r1, r1, #20 ; 0x14
0x67653734: ldr r12, [r3, #76]
0x67653738: ldr lr, [r12]
0x6765373c: str r7, [r5, #480]
0x67653740: str r2, [r4, #8]
0x67653744: sub r7, r6, #1 ; 0x1
0x67653748: str r7, [r4, #4]
0x6765374c: str r0, [r4, #20]
0x67653750: str r1, [r4, #28]
0x67653754: str r2, [r4, #44]
0x67653758: mov r0, r3
0x6765375c: mov r1, r12
0x67653760: mov r2, r5
0x67653764: bx lr
0x67653768: ldr r2, [r5, #4]
0x6765376c: cmp r2, #0 ; 0x0
0x67653770: movne r4, #0 ; 0x0
0x67653774: strne r4, [r5, #4]
0x67653778: strne r2, [r5, #4]
0x6765377c: ldrne r2, [r5, #484]
0x67653780: addne r4, r2, #12 ; 0xc
0x67653784: strne r4, [r5, #480]
0x67653788: ldrne r2, [r2]
0x6765378c: strne r2, [r5, #484]
0x67653790: ldreq r2, [r4, #8]
0x67653794: ldreq r4, [r5, #484]
0x67653798: addeq r0, r4, #8 ; 0x8
0x6765379c: streq r0, [r5, #480]
0x676537a0: ldreq r0, [r4]
0x676537a4: streq r0, [r5, #484]
0x676537a8: addeq r2, r6, r2
0x676537ac: streq r2, [r4, #8]
0x676537b0: pop {r4, r5, r6, r7, r11, pc}
0x676537b4: ldr r3, [pc, #168] ; 0x67653864
0x676537b8: ldr r3, [r3]
0x676537bc: cmp r3, #1 ; 0x1
0x676537c0: bne 0x6765382c
0x676537c4: add r3, r4, #12 ; 0xc
0x676537c8: str r3, [r5, #480]
0x676537cc: str r0, [r4, #20]
0x676537d0: add r0, r1, #21 ; 0x15
0x676537d4: str r0, [r4, #28]
0x676537d8: str r2, [r4, #44]
0x676537dc: ldr r2, [r5, #484]
0x676537e0: str r2, [r5, #256]
0x676537e4: mov r0, r5
0x676537e8: ldr r2, [pc, #120] ; 0x67653868
0x676537ec: bx r2
0x676537f0: mov r2, #0 ; 0x0
0x676537f4: str r2, [r5, #256]
0x676537f8: ldr r2, [r5, #4]
0x676537fc: cmp r2, #0 ; 0x0
0x67653800: movne r0, #0 ; 0x0
0x67653804: strne r0, [r5, #4]
0x67653808: strne r2, [r5, #4]
0x6765380c: ldrne r0, [r5, #484]
0x67653810: addne r1, r0, #12 ; 0xc
0x67653814: strne r1, [r5, #480]
0x67653818: ldrne r0, [r0]
0x6765381c: strne r0, [r5, #484]
0x67653820: popne {r4, r5, r6, r7, r11, pc}
0x67653824: ldr r2, [r4, #44]
0x67653828: ldr r2, [r4, #20]
0x6765382c: mov r2, #0 ; 0x0
0x67653830: ldr r0, [r5, #484]
0x67653834: add r1, r0, #8 ; 0x8
0x67653838: str r1, [r5, #480]
0x6765383c: ldr r1, [r0]
0x67653840: str r1, [r5, #484]
0x67653844: str r2, [r0, #8]
0x67653848: pop {r4, r5, r6, r7, r11, pc}
0x6765384c: ldr r0, [pc, #8] ; 0x6765385c
0x67653850: mov r1, #117 ; 0x75
0x67653854: ldr r4, [pc, #4] ; 0x67653860
0x67653858: bx r4
0x6765385c: adcmi r5, r0, r0, lsl #26
0x67653860: eormi r0, lr, r12, lsr #22
0x67653864: adcmi r12, r11, r8, lsl #14
0x67653868: submi r11, r8, r4, ror #17
0x6765386c: ldrsheq r9, [pc], -r2
0x67653870: strbvs r1, [sp, -r12, ror #31]!
0x67653874: strbvs r1, [sp, -r12, ror #31]!
0x67653878: andeq r0, r0, r0
0x6765387c: andeq r0, r0, r0
0x67653880: andeq r0, r0, r0
0x67653884: andeq r0, r0, r0
0x67653888: andeq r0, r0, r0
0x6765388c: andeq r0, r0, r0
0x67653890: andeq r0, r0, r0
(gdb) c
Continuing.
#
# A fatal error has been detected by the Java Runtime Environment:
#
# Internal Error (os_linux_zero.cpp:236), pid=17688, tid=1087521936
# Error: caught unhandled signal 11
#
# JRE version: 6.0_17-b17
# Java VM: OpenJDK Shark VM (14.0-b16 mixed mode linux-arm )
# An error report file with more information is saved as:
# /media/disk/test/cm30/hs_err_pid17688.log
#
# If you would like to submit a bug report, please include
# instructions how to reproduce the bug and visit:
# http://icedtea.classpath.org/bugzilla
#
Program received signal SIGABRT, Aborted.
########################################################## Dumped LLVM ir used
for in memory code generation.
# After PreEmit passes:
# Machine code for function MethodAtom::arithmeticSeries:
Frame Objects:
fi#0: size=4, align=4, at location [SP-4]
fi#1: size=4, align=4, at location [SP-8]
fi#2: size=4, align=4, at location [SP-12]
fi#3: size=4, align=4, at location [SP-16]
fi#4: size=4, align=4, at location [SP-20]
fi#5: size=4, align=4, at location [SP-24]
Constant Pool:
cp#0: i32 1084251392, align=4
cp#1: i32 1076759340, align=4
cp#2: i32 1084999432, align=4
cp#3: i32 1078507748, align=4
Function Live Ins: %R0 in reg%1036, %R1 in reg%1037, %R2 in reg%1038
BB#0: derived from LLVM BB %0
Live Ins: %R0 %R1 %R2 %LR %R11 %R7 %R6 %R5 %R4
STM %SP, 12, pred:14, pred:%reg0, %SP<def>, %R4<kill>, %R5<kill>,
%R6<kill>, %R7<kill>, %R11<kill>, %LR<kill>
%R12<def> = LDR %R2, %reg0, 480, pred:14, pred:%reg0;
mem:LD4[%stack_pointer_addr]
%R3<def> = LDR %R2, %reg0, 472, pred:14, pred:%reg0; mem:LD4[%7]
%R4<def> = SUBri %R12<kill>, 40, pred:14, pred:%reg0, opt:%reg0
CMPrr %R4, %R3<kill>, pred:14, pred:%reg0, %CPSR<imp-def>
Bcc <BB#6>, pred:3, pred:%CPSR
Successors according to CFG: BB#6 BB#1
BB#1: derived from LLVM BB %no_overflow
Live Ins: %R2 %R4 %R0 %R1
Predecessors according to CFG: BB#0
%R5<def> = MOVr %R2<kill>, pred:14, pred:%reg0, opt:%reg0
STR %R4, %R4, %reg0, 24, pred:14, pred:%reg0; mem:ST4[%9]
%R2<def> = MOVi 3, pred:14, pred:%reg0, opt:%reg0
STR %R2<kill>, %R4, %reg0, 32, pred:14, pred:%reg0; mem:ST4[%10]
%R2<def> = LDR %R5, %reg0, 484, pred:14, pred:%reg0;
mem:LD4[%frame_pointer_addr]
STR %R2<kill>, %R4, %reg0, 36, pred:14, pred:%reg0; mem:ST4[%11]
%R2<def> = ADDri %R4, 36, pred:14, pred:%reg0, opt:%reg0
STR %R2<kill>, %R5, %reg0, 484, pred:14, pred:%reg0;
mem:ST4[%frame_pointer_addr2]
%R6<def> = LDR %R4, %reg0, 40, pred:14, pred:%reg0; mem:LD4[%19]
%R2<def> = LDR %R4, %reg0, 44, pred:14, pred:%reg0; mem:LD4[%17]
CMPzri %R6, 0, pred:14, pred:%reg0, %CPSR<imp-def>
Bcc <BB#3>, pred:0, pred:%CPSR<kill>
Successors according to CFG: BB#2 BB#3
BB#2: derived from LLVM BB %bci_6
Live Ins: %R5 %R4 %R2 %R6 %R0 %R1
Predecessors according to CFG: BB#1
%R3<def> = LDR %R1, %reg0, 16, pred:14, pred:%reg0; mem:LD4[%25]
%R7<def> = ADDri %R4, 4, pred:14, pred:%reg0, opt:%reg0
%R1<def> = ADDri %R1<kill>, 20, pred:14, pred:%reg0, opt:%reg0
%R12<def> = LDR %R3, %reg0, 76, pred:14, pred:%reg0; mem:LD4[%28]
%LR<def> = LDR %R12, %reg0, 0, pred:14, pred:%reg0; mem:LD4[%30]
STR %R7<kill>, %R5, %reg0, 480, pred:14, pred:%reg0;
mem:ST4[%stack_pointer_addr5]
STR %R2, %R4, %reg0, 8, pred:14, pred:%reg0; mem:ST4[%36]
%R7<def> = SUBri %R6, 1, pred:14, pred:%reg0, opt:%reg0
STR %R7<kill>, %R4, %reg0, 4, pred:14, pred:%reg0; mem:ST4[%37]
STR %R0<kill>, %R4, %reg0, 20, pred:14, pred:%reg0; mem:ST4[%39]
STR %R1<kill>, %R4, %reg0, 28, pred:14, pred:%reg0; mem:ST4[%41]
STR %R2<kill>, %R4, %reg0, 44, pred:14, pred:%reg0; mem:ST4[%43]
%R0<def> = MOVr %R3<kill>, pred:14, pred:%reg0, opt:%reg0
%R1<def> = MOVr %R12<kill>, pred:14, pred:%reg0, opt:%reg0
%R2<def> = MOVr %R5, pred:14, pred:%reg0, opt:%reg0
BX %LR<kill>, %R0<kill>, %R1<kill>, %R2<kill>, %R0<imp-def,dead>,
%R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>,
%LR<imp-def,dead>, %CPSR<imp-def,dead>, ...
%R2<def> = LDR %R5, %reg0, 4, pred:14, pred:%reg0;
mem:LD4[%pending_exception_addr]
CMPzri %R2, 0, pred:14, pred:%reg0, %CPSR<imp-def>
%R4<def> = MOVi 0, pred:1, pred:%CPSR, opt:%reg0
STR %R4<kill>, %R5, %reg0, 4, pred:1, pred:%CPSR;
mem:ST4[%pending_exception_addr6]
STR %R2<kill>, %R5, %reg0, 4, pred:1, pred:%CPSR;
mem:ST4[%pending_exception_addr7]
%R2<def> = LDR %R5, %reg0, 484, pred:1, pred:%CPSR;
mem:LD4[%frame_pointer_addr8]
%R4<def> = ADDri %R2, 12, pred:1, pred:%CPSR, opt:%reg0
STR %R4<kill>, %R5, %reg0, 480, pred:1, pred:%CPSR;
mem:ST4[%stack_pointer_addr10]
%R2<def> = LDR %R2<kill>, %reg0, 0, pred:1, pred:%CPSR; mem:LD4[%61]
STR %R2<kill>, %R5<kill>, %reg0, 484, pred:1, pred:%CPSR;
mem:ST4[%frame_pointer_addr11]
%R2<def> = LDR %R4<kill>, %reg0, 8, pred:0, pred:%CPSR; mem:LD4[%44]
%R4<def> = LDR %R5, %reg0, 484, pred:0, pred:%CPSR;
mem:LD4[%frame_pointer_addr12]
%R0<def> = ADDri %R4, 8, pred:0, pred:%CPSR, opt:%reg0
STR %R0<kill>, %R5, %reg0, 480, pred:0, pred:%CPSR;
mem:ST4[%stack_pointer_addr14]
%R0<def> = LDR %R4, %reg0, 0, pred:0, pred:%CPSR; mem:LD4[%70]
STR %R0<kill>, %R5<kill>, %reg0, 484, pred:0, pred:%CPSR;
mem:ST4[%frame_pointer_addr15]
%R2<def> = ADDrr %R6<kill>, %R2<kill>, pred:0, pred:%CPSR, opt:%reg0
STR %R2<kill>, %R4<kill>, %reg0, 8, pred:0, pred:%CPSR; mem:ST4[%73]
LDM_RET %SP, 9, pred:14, pred:%reg0, %SP<def>, %R4<def>, %R5<def>,
%R6<def>, %R7<def>, %R11<def>, %PC<def>
Successors according to CFG: BB#7 BB#3
BB#3: derived from LLVM BB %bci_4
Live Ins: %R5 %R4 %R2 %R0 %R1
Predecessors according to CFG: BB#1 BB#2
%R3<def> = LDRcp <cp#2>, %reg0, 0, pred:14, pred:%reg0
%R3<def> = LDR %R3<kill>, %reg0, 0, pred:14, pred:%reg0;
mem:LD4[inttoptr (i32 1084999432 to i32*)]
CMPzri %R3<kill>, 1, pred:14, pred:%reg0, %CPSR<imp-def>
Bcc <BB#5>, pred:1, pred:%CPSR
Successors according to CFG: BB#4 BB#5
BB#4: derived from LLVM BB %do_safepoint
Live Ins: %R5 %R4 %R2 %R0 %R1
Predecessors according to CFG: BB#3
%R3<def> = ADDri %R4, 12, pred:14, pred:%reg0, opt:%reg0
STR %R3<kill>, %R5, %reg0, 480, pred:14, pred:%reg0;
mem:ST4[%stack_pointer_addr17]
STR %R0<kill>, %R4, %reg0, 20, pred:14, pred:%reg0; mem:ST4[%81]
%R0<def> = ADDri %R1<kill>, 21, pred:14, pred:%reg0, opt:%reg0
STR %R0<kill>, %R4, %reg0, 28, pred:14, pred:%reg0; mem:ST4[%83]
STR %R2<kill>, %R4, %reg0, 44, pred:14, pred:%reg0; mem:ST4[%85]
%R2<def> = LDR %R5, %reg0, 484, pred:14, pred:%reg0;
mem:LD4[%frame_pointer_addr18]
STR %R2<kill>, %R5, %reg0, 256, pred:14, pred:%reg0;
mem:ST4[%frame_anchor_addr]
%R0<def> = MOVr %R5, pred:14, pred:%reg0, opt:%reg0
%R2<def> = LDRcp <cp#3>, %reg0, 0, pred:14, pred:%reg0
BX %R2<kill>, %R0<kill>, %R0<imp-def,dead>, %R1<imp-def,dead>,
%R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>,
%CPSR<imp-def,dead>, ...
%R2<def> = MOVi 0, pred:14, pred:%reg0, opt:%reg0
STR %R2<kill>, %R5, %reg0, 256, pred:14, pred:%reg0;
mem:ST4[%frame_anchor_addr19]
%R2<def> = LDR %R5, %reg0, 4, pred:14, pred:%reg0;
mem:LD4[%pending_exception_addr22]
CMPzri %R2, 0, pred:14, pred:%reg0, %CPSR<imp-def>
%R0<def> = MOVi 0, pred:1, pred:%CPSR, opt:%reg0
STR %R0<kill>, %R5, %reg0, 4, pred:1, pred:%CPSR;
mem:ST4[%pending_exception_addr24]
STR %R2<kill>, %R5, %reg0, 4, pred:1, pred:%CPSR;
mem:ST4[%pending_exception_addr25]
%R0<def> = LDR %R5, %reg0, 484, pred:1, pred:%CPSR;
mem:LD4[%frame_pointer_addr26]
%R1<def> = ADDri %R0, 12, pred:1, pred:%CPSR, opt:%reg0
STR %R1<kill>, %R5, %reg0, 480, pred:1, pred:%CPSR;
mem:ST4[%stack_pointer_addr28]
%R0<def> = LDR %R0<kill>, %reg0, 0, pred:1, pred:%CPSR; mem:LD4[%114]
STR %R0<kill>, %R5<kill>, %reg0, 484, pred:1, pred:%CPSR;
mem:ST4[%frame_pointer_addr29]
LDM_RET %SP, 9, pred:1, pred:%CPSR, %SP<def>, %R4<def>, %R5<def>,
%R6<def>, %R7<def>, %R11<def>, %PC<def>
%R2<def,dead> = LDR %R4, %reg0, 44, pred:14, pred:%reg0; mem:LD4[%94]
%R2<def,dead> = LDR %R4<kill>, %reg0, 20, pred:14, pred:%reg0;
mem:LD4[%91]
Successors according to CFG: BB#5
BB#5: derived from LLVM BB %do_safepoint.safepointed_crit_edge
Live Ins: %D10 %D11 %D12 %D13 %D14 %D15 %D8 %D9 %R10 %R5 %R8 %R9 %S16 %S17
%S18 %S19 %S20 %S21 %S22 %S23 %S24 %S25 %S26 %S27 %S28 %S29 %S30 %S31
Predecessors according to CFG: BB#3 BB#4
%R2<def> = MOVi 0, pred:14, pred:%reg0, opt:%reg0
%R0<def> = LDR %R5, %reg0, 484, pred:14, pred:%reg0;
mem:LD4[%frame_pointer_addr31]
%R1<def> = ADDri %R0, 8, pred:14, pred:%reg0, opt:%reg0
STR %R1<kill>, %R5, %reg0, 480, pred:14, pred:%reg0;
mem:ST4[%stack_pointer_addr33]
%R1<def> = LDR %R0, %reg0, 0, pred:14, pred:%reg0; mem:LD4[%103]
STR %R1<kill>, %R5<kill>, %reg0, 484, pred:14, pred:%reg0;
mem:ST4[%frame_pointer_addr34]
STR %R2<kill>, %R0<kill>, %reg0, 8, pred:14, pred:%reg0; mem:ST4[%106]
LDM_RET %SP, 9, pred:14, pred:%reg0, %SP<def>, %R4<def>, %R5<def>,
%R6<def>, %R7<def>, %R11<def>, %PC<def>
BB#6: derived from LLVM BB %stack_overflow
Predecessors according to CFG: BB#0
%R0<def> = LDRcp <cp#0>, %reg0, 0, pred:14, pred:%reg0
%R1<def> = MOVi 117, pred:14, pred:%reg0, opt:%reg0
%R4<def> = LDRcp <cp#1>, %reg0, 0, pred:14, pred:%reg0
BX %R4<kill>, %R0<kill>, %R1<kill>, %R0<imp-def,dead>,
%R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>,
%LR<imp-def,dead>, %CPSR<imp-def,dead>, ...
BB#7: derived from LLVM BB %exception
Live Ins: %R5 %R2
Predecessors according to CFG: BB#2
BB#8:
CONSTPOOL_ENTRY 0, <cp#0>, 4
CONSTPOOL_ENTRY 1, <cp#1>, 4
CONSTPOOL_ENTRY 2, <cp#2>, 4
CONSTPOOL_ENTRY 3, <cp#3>, 4
# End machine code for function MethodAtom::arithmeticSeries.
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