OpenWrt/backfire + IcedTea + mips?

[Xerxes Ranby]

On 2011-04-08 14:19, John Connett wrote:
> Anyone tried this combination?  Any comments?
>
We need to add cross compilation support inside OpenJDK upstream or 
provided it from inside IcedTea in order to get IcedTea built by 
OpenWrt. You can find a summary of things needed to be done here:
https://blueprints.launchpad.net/linaro/+spec/java-crosscompiling-openjdk

... and of course integrate it all into OpenWRT so that you can select 
and add IcedTea/OpenJDK from the OpenWRT configure Languages/Utilities 
section.

> On my potential target:
> # cat /proc/cpuinfo
> system type             : Atheros AR9132 rev 2
> machine                 : Buffalo WZR-HP-G300NH

The Buffalo with 64Mb of RAM will be able to run some applications using 
OpenJDK fine.

The limited 32Mb of flash ROM storage will be a problem because OpenJDK 
needs glibc and thus the base system will need a quite large footprint. 
You can reduce the footprint somewhat by using eglibc. Also OpenJDK 
itself are massive and usually consumes around 140Mb.
If you put OpenJDK on a USB memory stick and occupy the USB port on the 
Buffalo then you will be fine.

If you use IcedTea to build OpenJDK then you can get a fast JVM with JIT 
running by building IcedTea using the --enable-cacao or --enable-jamvm 
configure options.

The IcedTea project are also hosting a brand new mips Hotspot JIT source 
repository that needs to be built and tested. This mips port was made to 
speed up OpenJDK for the Longsoon mips64, i do not know if it will work 
on mips32 but if it do then it are probably the fastest mips jvm port 
out there.
http://icedtea.classpath.org/hg/openjdk6-mips

Try to run prebuilt Debian mipsel openjdk binarys from inside your 
OpenWRT system to find out if the current available jvm's runs your 
intended applications fast enough and without hitting any out-of-memory 
senarios.

> processor               : 0
> cpu model               : MIPS 24Kc V7.4
> BogoMIPS                : 266.24
> wait instruction        : yes
> microsecond timers      : yes
> tlb_entries             : 16
> extra interrupt vector  : yes
> hardware watchpoint     : yes, count: 4, address/irw mask: [0x0000,
> 0x0000, 0x0020, 0x0048]
> ASEs implemented        : mips16
> shadow register sets    : 1
> core                    : 0
> VCED exceptions         : not available
> VCEI exceptions         : not available

Cheers
Xerxes