/hg/icedtea6: 6 new changesets
aph at icedtea.classpath.org
aph at icedtea.classpath.org
Thu Dec 8 02:10:07 PST 2011
changeset b792105e5b1a in /hg/icedtea6
details: http://icedtea.classpath.org/hg/icedtea6?cmd=changeset;node=b792105e5b1a
author: aph
date: Fri Dec 02 13:28:02 2011 -0500
The big volatile patch.
changeset c3830a06fd60 in /hg/icedtea6
details: http://icedtea.classpath.org/hg/icedtea6?cmd=changeset;node=c3830a06fd60
author: aph
date: Mon Dec 05 10:32:03 2011 -0500
More volatile fixups.
changeset 7818ff550f62 in /hg/icedtea6
details: http://icedtea.classpath.org/hg/icedtea6?cmd=changeset;node=7818ff550f62
author: aph
date: Mon Dec 05 10:48:00 2011 -0500
More volatile tidying-up.
changeset 3ca12f50fff3 in /hg/icedtea6
details: http://icedtea.classpath.org/hg/icedtea6?cmd=changeset;node=3ca12f50fff3
author: aph
date: Tue Dec 06 06:17:49 2011 -0500
Volatile rewrite. 011-12-05 Andrew Haley <aph at redhat.com>
* arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp
(Thumb2_disass): Use class Opcodes to do the disassembly.
(Thumb2_Enter): Update ISTATE_SELF_LINK. (T_DMB): New.
(fullBarrier): New. (storeBarrier): New.
(Thumb2_Accessor): Add volatile barriers. (Thumb2_codegen):
Likewise. (Thumb2_Initialize): Check UseCompiler.
(class Opcodes): New. Load libopcodes.so lazily.
* arm_port/hotspot/src/cpu/zero/vm/bytecodes_arm.def: For every
{get,put}field handler, add a test for volatility and duplicate
the code path into two parts, volatile and non-volatile. Add
barriers to the volatile path.
* arm_port/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S (dmb)
(dmb_st): New macros. (abort_table): Add entries for
volatile versions of all the field handlers.
({put,get}field_volatile_*): Add volatile versions of all handlers.
(Thumb2_{put,get}field_*_stub): Likewise.
* arm_port/hotspot/src/cpu/zero/vm/asm_helper.cpp
(print_vm_offsets): Add CP_CACHE_VOLATILE_FIELD_FLAG_BIT and
CP_CACHE_FLAGS.
changeset 357ee1a7d452 in /hg/icedtea6
details: http://icedtea.classpath.org/hg/icedtea6?cmd=changeset;node=357ee1a7d452
author: aph
date: Wed Dec 07 18:14:25 2011 +0000
xranby's suggested improvements.
changeset 6a04d4888cc0 in /hg/icedtea6
details: http://icedtea.classpath.org/hg/icedtea6?cmd=changeset;node=6a04d4888cc0
author: aph
date: Thu Dec 08 10:09:28 2011 +0000
merge
diffstat:
ChangeLog | 42 ++
Makefile.am | 4 +-
NEWS | 2 +
arm_port/hotspot/src/cpu/zero/vm/asm_helper.cpp | 2 +
arm_port/hotspot/src/cpu/zero/vm/bytecodes_arm.def | 168 ++++++++
arm_port/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S | 341 +++++++++++++++++-
arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp | 95 ++++-
7 files changed, 643 insertions(+), 11 deletions(-)
diffs (truncated from 1326 to 500 lines):
diff -r 0a0072170876 -r 6a04d4888cc0 ChangeLog
--- a/ChangeLog Mon Nov 28 20:06:41 2011 +0000
+++ b/ChangeLog Thu Dec 08 10:09:28 2011 +0000
@@ -1,3 +1,45 @@
+2011-12-07 Andrew Haley <aph at redhat.com>
+
+ * arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp
+ (Thumb2_disass): Use class Opcodes to do the disassembly.
+ (Thumb2_Enter): Update ISTATE_SELF_LINK.
+ (T_DMB): New.
+ (fullBarrier): New.
+ (storeBarrier): New.
+ (Thumb2_Accessor): Add volatile barriers.
+ (Thumb2_codegen): Likewise.
+ (Thumb2_Initialize): Check UseCompiler.
+ (class Opcodes): New. Load libopcodes.so lazily.
+ * arm_port/hotspot/src/cpu/zero/vm/bytecodes_arm.def: For every
+ {get,put}field handler, add a test for volatility and duplicate
+ the code path into two parts, volatile and non-volatile. Add
+ barriers to the volatile path.
+ * arm_port/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S (dmb)
+ (dmb_st, FullBarrier, StoreLoadBarrier, StoreStoreBarrier): New
+ macros.
+ (abort_table): Add entries for volatile versions of all the field
+ handlers.
+ ({put,get}field_volatile_*): Add volatile versions of all handlers.
+ (Thumb2_{put,get}field_*_stub): Likewise.
+ * arm_port/hotspot/src/cpu/zero/vm/asm_helper.cpp
+ (print_vm_offsets): Add CP_CACHE_VOLATILE_FIELD_FLAG_BIT and
+ CP_CACHE_FLAGS.
+
+2011-12-06 Xerxes RÃ¥nby <xerxes at zafena.se>
+
+ CACAO:
+ - CA162: Make class init protection aware of multiple threads.
+ - CA163: descriptor_params_from_paramtypes is protected by a mutex now.
+ - Removed return value from descriptor_params_from_paramtypes.
+ - Removed fields from classinfo and related functions from
+ descriptor pool.
+ - src/vm/jit/jit.cpp: Eliminate one instance of useless cache flushing.
+ * NEWS:
+ Updated.
+ * Makefile.am:
+ (CACAO_VERSION): Updated CACAO to 2011-12-01 revision.
+ (CACAO_SHA256SUM): Updated.
+
2011-11-28 Andrew John Hughes <ahughes at redhat.com>
* NEWS:
diff -r 0a0072170876 -r 6a04d4888cc0 Makefile.am
--- a/Makefile.am Mon Nov 28 20:06:41 2011 +0000
+++ b/Makefile.am Thu Dec 08 10:09:28 2011 +0000
@@ -5,8 +5,8 @@
OPENJDK_VERSION = b24
OPENJDK_URL = http://download.java.net/openjdk/jdk6/promoted/$(OPENJDK_VERSION)/
-CACAO_VERSION = 2204b08fcae9
-CACAO_SHA256SUM = bb6ce286fcdc7350ed9913acfe5177921f515e187e74e773f6e62adba005f0a3
+CACAO_VERSION = ea0e1b9ccf8d
+CACAO_SHA256SUM = cce66fecc290f3f7450a0463e460959028e6c81b0d7b130bb6c54bcbccf39efe
CACAO_BASE_URL = http://icedtea.classpath.org/download/drops/cacao
CACAO_URL = $(CACAO_BASE_URL)/$(CACAO_VERSION).tar.gz
CACAO_SRC_ZIP = cacao-$(CACAO_VERSION).tar.gz
diff -r 0a0072170876 -r 6a04d4888cc0 NEWS
--- a/NEWS Mon Nov 28 20:06:41 2011 +0000
+++ b/NEWS Thu Dec 08 10:09:28 2011 +0000
@@ -387,6 +387,8 @@
* CACAO
- CA149: Used wrong class loader.
- CA159: Exception handler blocks / register mixup.
+ - CA162: Make class init protection aware of multiple threads.
+ - CA163: descriptor_params_from_paramtypes is protected by a mutex now.
- ARM: Remove broken support for float argument passing in registers.
- ARM: Remove hack for return value in float registers.
- ARM: Fixed use of uninitialized variable.
diff -r 0a0072170876 -r 6a04d4888cc0 arm_port/hotspot/src/cpu/zero/vm/asm_helper.cpp
--- a/arm_port/hotspot/src/cpu/zero/vm/asm_helper.cpp Mon Nov 28 20:06:41 2011 +0000
+++ b/arm_port/hotspot/src/cpu/zero/vm/asm_helper.cpp Thu Dec 08 10:09:28 2011 +0000
@@ -489,6 +489,8 @@
print_def("CONSTANTPOOL_CACHE", offset_of(constantPoolOopDesc, _cache));
print_def("CONSTANTPOOL_POOL_HOLDER", offset_of(constantPoolOopDesc, _pool_holder));
print_def("CONSTANTPOOL_BASE", sizeof(constantPoolOopDesc));
+ print_def("CP_CACHE_VOLATILE_FIELD_FLAG_BIT", ConstantPoolCacheEntry::volatileField);
+ print_def("CP_CACHE_FLAGS", offset_of(ConstantPoolCacheEntry, _flags));
nl();
print_def("CP_OFFSET", in_bytes(constantPoolCacheOopDesc::base_offset()));
nl();
diff -r 0a0072170876 -r 6a04d4888cc0 arm_port/hotspot/src/cpu/zero/vm/bytecodes_arm.def
--- a/arm_port/hotspot/src/cpu/zero/vm/bytecodes_arm.def Mon Nov 28 20:06:41 2011 +0000
+++ b/arm_port/hotspot/src/cpu/zero/vm/bytecodes_arm.def Thu Dec 08 10:09:28 2011 +0000
@@ -1573,6 +1573,7 @@
DISPATCH_NEXT
SW_NPC cmp tmp1, #0
SW_NPC beq null_ptr_exception_jpc_3
+ GO_IF_VOLATILE r3, tmp2, 3f
ldr tmp2, [tmp2, #CP_OFFSET+8]
DISPATCH_NEXT
.abortentry78:
@@ -1581,6 +1582,17 @@
DISPATCH_NEXT
PUSH tmp2
DISPATCH_FINISH
+3:
+ VOLATILE_VERSION
+ ldr tmp2, [tmp2, #CP_OFFSET+8]
+ DISPATCH_NEXT
+.abortentry78_v:
+ ldr tmp2, [tmp1, tmp2]
+ FullBarrier
+ DISPATCH_NEXT
+ DISPATCH_NEXT
+ PUSH tmp2
+ DISPATCH_FINISH
}
(bgetfield) bgetfield {
@@ -1592,6 +1604,7 @@
DISPATCH_NEXT
SW_NPC cmp tmp1, #0
SW_NPC beq null_ptr_exception_jpc_3
+ GO_IF_VOLATILE r3, tmp2, 3f
ldr tmp2, [tmp2, #CP_OFFSET+8]
DISPATCH_NEXT
.abortentry79:
@@ -1600,6 +1613,17 @@
DISPATCH_NEXT
PUSH tmp2
DISPATCH_FINISH
+3:
+ VOLATILE_VERSION
+ ldr tmp2, [tmp2, #CP_OFFSET+8]
+ DISPATCH_NEXT
+.abortentry79_v:
+ ldrsb tmp2, [tmp1, tmp2]
+ FullBarrier
+ DISPATCH_NEXT
+ DISPATCH_NEXT
+ PUSH tmp2
+ DISPATCH_FINISH
}
(cgetfield) cgetfield {
@@ -1611,6 +1635,7 @@
DISPATCH_NEXT
SW_NPC cmp tmp1, #0
SW_NPC beq null_ptr_exception_jpc_3
+ GO_IF_VOLATILE r3, tmp2, 3f
ldr tmp2, [tmp2, #CP_OFFSET+8]
DISPATCH_NEXT
.abortentry80:
@@ -1619,6 +1644,17 @@
DISPATCH_NEXT
PUSH tmp2
DISPATCH_FINISH
+3:
+ VOLATILE_VERSION
+ ldr tmp2, [tmp2, #CP_OFFSET+8]
+ DISPATCH_NEXT
+.abortentry80_v:
+ ldrh tmp2, [tmp1, tmp2]
+ FullBarrier
+ DISPATCH_NEXT
+ DISPATCH_NEXT
+ PUSH tmp2
+ DISPATCH_FINISH
}
(sgetfield) sgetfield {
@@ -1630,6 +1666,7 @@
DISPATCH_NEXT
SW_NPC cmp tmp1, #0
SW_NPC beq null_ptr_exception_jpc_3
+ GO_IF_VOLATILE r3, tmp2, 3f
ldr tmp2, [tmp2, #CP_OFFSET+8]
DISPATCH_NEXT
.abortentry81:
@@ -1638,6 +1675,17 @@
DISPATCH_NEXT
PUSH tmp2
DISPATCH_FINISH
+3:
+ VOLATILE_VERSION
+ ldr tmp2, [tmp2, #CP_OFFSET+8]
+ DISPATCH_NEXT
+.abortentry81_v:
+ ldrsh tmp2, [tmp1, tmp2]
+ FullBarrier
+ DISPATCH_NEXT
+ DISPATCH_NEXT
+ PUSH tmp2
+ DISPATCH_FINISH
}
(lgetfield) lgetfield {
@@ -1649,6 +1697,7 @@
DISPATCH_NEXT
SW_NPC cmp tmp1, #0
SW_NPC beq null_ptr_exception_jpc_3
+ GO_IF_VOLATILE r3, tmp2, 3f
ldr tmp2, [tmp2, #CP_OFFSET+8]
DISPATCH_NEXT
add tmp2, tmp1, tmp2
@@ -1658,6 +1707,18 @@
DISPATCH_NEXT
PUSH tmp2, tmp1
DISPATCH_FINISH
+3:
+ VOLATILE_VERSION
+ ldr tmp2, [tmp2, #CP_OFFSET+8]
+ DISPATCH_NEXT
+ add tmp2, tmp1, tmp2
+ DISPATCH_NEXT
+.abortentry82_v:
+ ldmia tmp2, {tmp2, tmp1}
+ FullBarrier
+ DISPATCH_NEXT
+ PUSH tmp2, tmp1
+ DISPATCH_FINISH
}
(iputfield) iputfield {
@@ -1669,6 +1730,7 @@
DISPATCH_NEXT
SW_NPC cmp tmp1, #0
SW_NPC beq null_ptr_exception_jpc_3
+ GO_IF_VOLATILE r2, tmp2, 3f
ldr tmp2, [tmp2, #CP_OFFSET+8]
DISPATCH_NEXT
DISPATCH_NEXT
@@ -1676,6 +1738,17 @@
.abortentry83:
str r3, [tmp1, tmp2]
DISPATCH_FINISH
+3:
+ VOLATILE_VERSION
+ ldr tmp2, [tmp2, #CP_OFFSET+8]
+ DISPATCH_NEXT
+ DISPATCH_NEXT
+ DISPATCH_NEXT
+ StoreStoreBarrier
+.abortentry83_v:
+ str r3, [tmp1, tmp2]
+ StoreLoadBarrier
+ DISPATCH_FINISH
}
(cputfield) cputfield {
@@ -1687,6 +1760,7 @@
DISPATCH_NEXT
SW_NPC cmp tmp1, #0
SW_NPC beq null_ptr_exception_jpc_3
+ GO_IF_VOLATILE r2, tmp2, 3f
ldr tmp2, [tmp2, #CP_OFFSET+8]
DISPATCH_NEXT
DISPATCH_NEXT
@@ -1694,6 +1768,17 @@
.abortentry84:
strh r3, [tmp1, tmp2]
DISPATCH_FINISH
+3:
+ VOLATILE_VERSION
+ ldr tmp2, [tmp2, #CP_OFFSET+8]
+ DISPATCH_NEXT
+ DISPATCH_NEXT
+ DISPATCH_NEXT
+ StoreStoreBarrier
+.abortentry84_v:
+ strh r3, [tmp1, tmp2]
+ StoreLoadBarrier
+ DISPATCH_FINISH
}
(bputfield) bputfield {
@@ -1705,6 +1790,7 @@
DISPATCH_NEXT
SW_NPC cmp tmp1, #0
SW_NPC beq null_ptr_exception_jpc_3
+ GO_IF_VOLATILE r2, tmp2, 3f
ldr tmp2, [tmp2, #CP_OFFSET+8]
DISPATCH_NEXT
DISPATCH_NEXT
@@ -1712,6 +1798,17 @@
.abortentry85:
strb r3, [tmp1, tmp2]
DISPATCH_FINISH
+3:
+ VOLATILE_VERSION
+ ldr tmp2, [tmp2, #CP_OFFSET+8]
+ DISPATCH_NEXT
+ DISPATCH_NEXT
+ DISPATCH_NEXT
+ StoreStoreBarrier
+.abortentry85_v:
+ strb r3, [tmp1, tmp2]
+ StoreLoadBarrier
+ DISPATCH_FINISH
}
(aputfield) aputfield {
@@ -1721,12 +1818,23 @@
add tmp2, tmp2, r2, lsl #4
SW_NPC cmp tmp1, #0
SW_NPC beq null_ptr_exception_jpc_3
+ GO_IF_VOLATILE r2, tmp2, 3f
ldr tmp2, [tmp2, #CP_OFFSET+8]
.abortentry113:
str r3, [tmp1, tmp2]
mov r0, tmp1
bl Helper_aputfield
DISPATCH 3
+3:
+ VOLATILE_VERSION
+ ldr tmp2, [tmp2, #CP_OFFSET+8]
+ StoreStoreBarrier
+.abortentry113_v:
+ str r3, [tmp1, tmp2]
+ StoreLoadBarrier
+ mov r0, tmp1
+ bl Helper_aputfield
+ DISPATCH 3
}
(lputfield) lputfield {
@@ -1738,6 +1846,7 @@
DISPATCH_NEXT
SW_NPC cmp lr, #0
SW_NPC beq null_ptr_exception_jpc_3
+ GO_IF_VOLATILE r2, tmp2, 3f
ldr tmp2, [tmp2, #CP_OFFSET+8]
DISPATCH_NEXT
add tmp2, lr, tmp2
@@ -1746,6 +1855,18 @@
.abortentry86:
stm tmp2, {r3, tmp1}
DISPATCH_FINISH
+3:
+ VOLATILE_VERSION
+ ldr tmp2, [tmp2, #CP_OFFSET+8]
+ DISPATCH_NEXT
+ add tmp2, lr, tmp2
+ DISPATCH_NEXT
+ DISPATCH_NEXT
+ StoreStoreBarrier
+.abortentry86_v:
+ stm tmp2, {r3, tmp1}
+ StoreLoadBarrier
+ DISPATCH_FINISH
}
#endif // FAST_BYTECODES
@@ -1760,6 +1881,7 @@
and r3, r3, #0x00ff0000
cmp r3, #opc_getstatic << 16
blne resolve_get_put
+ GO_IF_VOLATILE r2, tmp2, 3f
ldr r3, [tmp2, #CP_OFFSET+4]
ldr r2, [tmp2, #CP_OFFSET+12]
ldr lr, [tmp2, #CP_OFFSET+8]
@@ -1770,6 +1892,18 @@
tst r2, #2
bne getstatic_dw
b getstatic_sh
+3:
+ VOLATILE_VERSION
+ ldr r3, [tmp2, #CP_OFFSET+4]
+ ldr r2, [tmp2, #CP_OFFSET+12]
+ ldr lr, [tmp2, #CP_OFFSET+8]
+ movs r2, r2, lsr #29
+ bhi getstatic_volatile_w @ C = 1, Z = 0 => R2 == 3, 5, 7
+ bcs getstatic_volatile_h @ C = 1 => R2 = 1
+ beq getstatic_volatile_sb @ Z = 1 => R2 = 0
+ tst r2, #2
+ bne getstatic_volatile_dw
+ b getstatic_volatile_sh
}
@ r2 = [jpc, #1]
@@ -1782,6 +1916,7 @@
and r3, r3, #0xff000000
cmp r3, #opc_putstatic << 24
blne resolve_get_put
+ GO_IF_VOLATILE r2, tmp2, 3f
ldr r3, [tmp2, #CP_OFFSET+4] @ r3 = object
ldr lr, [tmp2, #CP_OFFSET+12] @ lr = tos_type
ldr r2, [tmp2, #CP_OFFSET+8] @ r2 = offset
@@ -1792,6 +1927,18 @@
tst lr, #2
bne putstatic_dw
b putstatic_sh
+3:
+ VOLATILE_VERSION
+ ldr r3, [tmp2, #CP_OFFSET+4] @ r3 = object
+ ldr lr, [tmp2, #CP_OFFSET+12] @ lr = tos_type
+ ldr r2, [tmp2, #CP_OFFSET+8] @ r2 = offset
+ movs lr, lr, lsr #29
+ bhi putstatic_volatile_w @ C = 1, Z = 0 => R2 == 3, 5, 7
+ bcs putstatic_volatile_h @ C = 1 => R2 = 1
+ beq putstatic_volatile_sb @ Z = 1 => R2 = 0
+ tst lr, #2
+ bne putstatic_volatile_dw
+ b putstatic_volatile_sh
}
#ifdef NOTICE_SAFEPOINTS
@@ -2216,6 +2363,7 @@
DISPATCH_NEXT
SW_NPC cmp tmp1, #0
SW_NPC beq null_ptr_exception_jpc_3
+ GO_IF_VOLATILE r3, tmp2, 3f
DISPATCH_NEXT
ldr tmp2, [tmp2, #CP_OFFSET+8]
DISPATCH_NEXT
@@ -2224,6 +2372,16 @@
DISPATCH_NEXT
PUSH tmp2
DISPATCH_FINISH
+3:
+ VOLATILE_VERSION
+ DISPATCH_NEXT
+ ldr tmp2, [tmp2, #CP_OFFSET+8]
+ DISPATCH_NEXT
+.abortentry87_v:
+ ldr tmp2, [tmp1, tmp2]
+ DISPATCH_NEXT
+ PUSH tmp2
+ DISPATCH_FINISH
}
@ r2 = [jpc, #1]
@@ -4086,6 +4244,7 @@
SW_NPC cmp tmp1, #0
SW_NPC beq null_ptr_exception_jpc_3
DISPATCH_NEXT
+ GO_IF_VOLATILE r3, tmp2, 3f
ldr tmp2, [tmp2, #CP_OFFSET+8]
DISPATCH_NEXT
.abortentry88:
@@ -4093,6 +4252,15 @@
DISPATCH_NEXT
PUSH tmp2
DISPATCH_FINISH
+3:
+ VOLATILE_VERSION
+ ldr tmp2, [tmp2, #CP_OFFSET+8]
+ DISPATCH_NEXT
+.abortentry88_v:
+ ldr tmp2, [tmp1, tmp2]
+ DISPATCH_NEXT
+ PUSH tmp2
+ DISPATCH_FINISH
}
@ --- iconst; store -------------------------------------------------
diff -r 0a0072170876 -r 6a04d4888cc0 arm_port/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S
--- a/arm_port/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S Mon Nov 28 20:06:41 2011 +0000
+++ b/arm_port/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S Thu Dec 08 10:09:28 2011 +0000
@@ -529,6 +529,7 @@
ldrb r1, [jpc, lr]
bic ip, ip, #7
ldr pc, [ip, r1, lsl #2]
+ .ltorg
.endm
#define FFI_TYPE_VOID 0
@@ -585,6 +586,45 @@
.fpu softvfp
#endif // HW_FP
+#ifndef __ARM_ARCH_7A__
+# define dmb VOLATILE_BARRIER
+# define dmb_st VOLATILE_BARRIER
+#else
+# define dmb_st .inst 0xf57ff05e
+#endif
+
+#define StoreStoreBarrier dmb_st
+#define StoreLoadBarrier dmb
+#define FullBarrier dmb
+
+ .macro VOLATILE_BARRIER arg
+ stmfd sp!, {r2, lr}
+ ldr r2, =0xffff0fa0 @ kernel_dmb
+ blx r2
+ ldmfd sp!, {r2, lr}
+ .endm
+
+ .macro GO_IF_VOLATILE reg, cp_cache, label
+ ldr \reg, [\cp_cache, #CP_OFFSET+CP_CACHE_FLAGS]
+ tst \reg, #(1<<CP_CACHE_VOLATILE_FIELD_FLAG_BIT)
+ bne \label
+ .set dispatch_saved, dispatch_state
+ .endm
+
+ @ We have to save and restore the dispatch_state because
+ @ dispatching is done twice, once each for volatile and
+ @ non-volatile versions. It's essential that dispatch_state
+ @ be correct at the entry to the volatile version of the
+ @ handler.
+
+ .macro VOLATILE_VERSION
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