/hg/icedtea6: 6 new changesets
aph at icedtea.classpath.org
aph at icedtea.classpath.org
Tue Dec 20 10:49:22 PST 2011
changeset 8fa75d2623a2 in /hg/icedtea6
details: http://icedtea.classpath.org/hg/icedtea6?cmd=changeset;node=8fa75d2623a2
author: aph
date: Mon Dec 19 10:56:30 2011 -0500
Safepoints for ARM JIT-compiled code. 2011-12-16 Andrew Haley
<aph at redhat.com>
* arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp (H_SAFEPOINT):
New. (Thumb2_Safepoint): New. (Thumb2_Branch): Call
Thumb2_Safepoint. (Thumb2_Goto): Likewise.
(Thumb2_Return): Likewise. (Thumb2_Initialize): Add handler
for H_SAFEPOINT.
changeset 0c874e429552 in /hg/icedtea6
details: http://icedtea.classpath.org/hg/icedtea6?cmd=changeset;node=0c874e429552
author: aph
date: Mon Dec 19 16:04:36 2011 +0000
merge
changeset fd44d23e1368 in /hg/icedtea6
details: http://icedtea.classpath.org/hg/icedtea6?cmd=changeset;node=fd44d23e1368
author: aph
date: Mon Dec 19 13:05:45 2011 -0500
Add atomic sequences using ldrexd/strexd. 2011-12-19 Andrew Haley
<aph at redhat.com>
* arm_port/hotspot/src/cpu/zero/vm/bytecodes_arm.def
(lgetfield, lputfield): Add atomic sequences using ldrexd/strexd.
* openjdk-ecj/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S
(getstatic_volatile_dw, putstatic_volatile_dw): Likewise.
changeset 293b2d68ce5f in /hg/icedtea6
details: http://icedtea.classpath.org/hg/icedtea6?cmd=changeset;node=293b2d68ce5f
author: aph
date: Tue Dec 20 10:12:28 2011 -0500
PR837: Fix copying to srcdir on a different physical device.
2011-12-20 Andrew Haley <aph at redhat.com>
PR837:
* Makefile.am (stamps/ports.stamp): Replace "cp -l" with "cp
$(SRC_DIR_LINK)".
changeset c4c8d17de1e2 in /hg/icedtea6
details: http://icedtea.classpath.org/hg/icedtea6?cmd=changeset;node=c4c8d17de1e2
author: aph
date: Tue Dec 20 15:36:52 2011 +0000
Generate atomic sequences for volatile long field accesses.
2011-12-20 Andrew Haley <aph at redhat.com>
* openjdk/hotspot/src/cpu/zero/vm/thumb2.cpp (T_LDREXD,
T_STREXD): New instructions. (ldrexd, strexd):
Likewise. (Thumb2_load_long, Thumb2_store_long): New
functions. (Thumb2_codegen): Use Thumb2_load_long and
Thumb2_store_long for all long field accesses.
changeset cf80d2049346 in /hg/icedtea6
details: http://icedtea.classpath.org/hg/icedtea6?cmd=changeset;node=cf80d2049346
author: aph
date: Tue Dec 20 13:49:11 2011 -0500
merge
diffstat:
ChangeLog | 51 +
Makefile.am | 5 +-
NEWS | 2 +
arm_port/hotspot/src/cpu/zero/vm/bytecodes_arm.def | 28 +-
arm_port/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S | 26 +-
arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp | 160 +++++-
patches/openjdk/7102369-7094468-rmiregistry.patch | 466 ++++++++++++++++++
7 files changed, 714 insertions(+), 24 deletions(-)
diffs (truncated from 983 to 500 lines):
diff -r d6cf8b242032 -r cf80d2049346 ChangeLog
--- a/ChangeLog Mon Dec 12 12:46:59 2011 -0500
+++ b/ChangeLog Tue Dec 20 13:49:11 2011 -0500
@@ -1,3 +1,54 @@
+2011-12-20 Andrew Haley <aph at redhat.com>
+
+ * arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp (T_LDREXD, T_STREXD):
+ New instructions.
+ (ldrexd, strexd): Likewise.
+ (Thumb2_load_long, Thumb2_store_long): New functions.
+ (Thumb2_codegen): Use Thumb2_load_long and Thumb2_store_long for
+ all long field accesses.
+
+2011-12-20 Andrew Haley <aph at redhat.com>
+
+ PR837:
+ * Makefile.am (stamps/ports.stamp): Replace "cp -l" with
+ "cp $(SRC_DIR_LINK)".
+
+2011-12-19 Andrew Haley <aph at redhat.com>
+
+ * arm_port/hotspot/src/cpu/zero/vm/bytecodes_arm.def
+ (lgetfield, lputfield): Add atomic sequences using ldrexd/strexd.
+ * arm_port/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S
+ (getstatic_volatile_dw, putstatic_volatile_dw): Likewise.
+
+2011-12-16 Andrew Haley <aph at redhat.com>
+
+ * arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp (H_SAFEPOINT): New.
+ (Thumb2_Safepoint): New.
+ (Thumb2_Branch): Call Thumb2_Safepoint.
+ (Thumb2_Goto): Likewise.
+ (Thumb2_Return): Likewise.
+ (Thumb2_Initialize): Add handler for H_SAFEPOINT.
+
+2011-12-16 Matthias Klose <doko at ubuntu.com>
+
+ * Makefile.am (JTREG_SRCS, REWRITER_SRCS, EXTRA_DIST): Don't use any
+ prefixes.
+ (stamps/jtreg.stamp, check-jdk): Use JTREG_SRCS with srcdir prefix.
+ (stamps/rewriter.stamp): Use REWRITER_SRCS with srcdir prefix.
+
+2011-12-16 Xerxes RÃ¥nby <xerxes at zafena.se>
+
+ * arm_port/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S
+ (.fast_native_return_dw): Add a missing PR484 return 0.
+
+2011-12-12 Omair Majid <omajid at redhat.com>
+
+ S7102369, S7094468: remove java.rmi.server.codebase property
+ parsing from rmiregistry
+ * patches/openjdk/7102369-7094468-rmiregistry.patch: New
+ file. Backport from OpenJDK6.
+ * Makefile.am (ICEDTEA_PATCHES): Apply the patch.
+
2011-12-12 Andrew Haley <aph at redhat.com>
* arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp (DisableCompiler): Delete.
diff -r d6cf8b242032 -r cf80d2049346 Makefile.am
--- a/Makefile.am Mon Dec 12 12:46:59 2011 -0500
+++ b/Makefile.am Tue Dec 20 13:49:11 2011 -0500
@@ -397,7 +397,8 @@
patches/openjdk/6296893-BMP_Writer_handles_TopDown_prop_incorrectly.patch \
patches/openjdk/7103224-glibc_name_collision.patch \
patches/arm-debug.patch \
- patches/openjdk/683768-System-tray-icon.patch
+ patches/openjdk/683768-System-tray-icon.patch \
+ patches/openjdk/7102369-7094468-rmiregistry.patch
if WITH_RHINO
ICEDTEA_PATCHES += \
@@ -1033,7 +1034,7 @@
for target in $(abs_top_srcdir)/arm_port/hotspot/tools \
$(abs_top_srcdir)/arm_port/hotspot/src/*cpu/* ; do \
link=$$(dirname $$target | sed 's/^.*arm_port/openjdk/'); \
- cp -rlv $$target $$link; \
+ cp -rv $(SRC_DIR_LINK) $$target $$link; \
chmod -R ug+rwX $$link; \
done
mkdir -p stamps
diff -r d6cf8b242032 -r cf80d2049346 NEWS
--- a/NEWS Mon Dec 12 12:46:59 2011 -0500
+++ b/NEWS Tue Dec 20 13:49:11 2011 -0500
@@ -383,6 +383,8 @@
- S5082756: Image I/O plug-ins set metadata boolean attributes to "true" or "false"
- S6296893: BMP Writer handles TopDown property incorrectly for some of the compression types
- S7103224: collision between __LEAF define in interfaceSupport.hpp and /usr/include/sys/cdefs.h with gcc
+ - S7102369: remove java.rmi.server.codebase property parsing from registyimpl
+ - S7094468: rmiregistry clean up
* Allow selection of test suites using the jtreg_checks argument e.g. jtreg_checks="langtools"
* CACAO
- CA149: Used wrong class loader.
diff -r d6cf8b242032 -r cf80d2049346 arm_port/hotspot/src/cpu/zero/vm/bytecodes_arm.def
--- a/arm_port/hotspot/src/cpu/zero/vm/bytecodes_arm.def Mon Dec 12 12:46:59 2011 -0500
+++ b/arm_port/hotspot/src/cpu/zero/vm/bytecodes_arm.def Tue Dec 20 13:49:11 2011 -0500
@@ -1710,11 +1710,19 @@
3:
VOLATILE_VERSION
ldr tmp2, [tmp2, #CP_OFFSET+8]
- DISPATCH_NEXT
add tmp2, tmp1, tmp2
- DISPATCH_NEXT
+#ifndef __ARM_ARCH_7A__
.abortentry82_v:
ldmia tmp2, {tmp2, tmp1}
+#else
+ mov ip, tmp2
+.abortentry82_v:
+ ldrexd tmp2, tmp1 , [ip]
+ strexd r2 , tmp2, tmp1, [ip]
+ teq r2, #0
+ bne .abortentry82_v
+#endif
+ DISPATCH_NEXT
FullBarrier
DISPATCH_NEXT
PUSH tmp2, tmp1
@@ -1858,13 +1866,23 @@
3:
VOLATILE_VERSION
ldr tmp2, [tmp2, #CP_OFFSET+8]
- DISPATCH_NEXT
add tmp2, lr, tmp2
- DISPATCH_NEXT
- DISPATCH_NEXT
StoreStoreBarrier
+#ifndef __ARM_ARCH_7A__
.abortentry86_v:
stm tmp2, {r3, tmp1}
+#else
+ mov ip, tmp2
+ mov tmp2, r3
+ // Data in tmp1 & tmp2, address in ip, r2 & r3 scratch
+.abortentry86_v:
+ ldrexd r2, r3, [ip]
+ strexd r2, tmp2, tmp1, [ip]
+ teq r2, #0
+ bne .abortentry86_v
+#endif
+ DISPATCH_NEXT
+ DISPATCH_NEXT
StoreLoadBarrier
DISPATCH_FINISH
}
diff -r d6cf8b242032 -r cf80d2049346 arm_port/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S
--- a/arm_port/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S Mon Dec 12 12:46:59 2011 -0500
+++ b/arm_port/hotspot/src/cpu/zero/vm/cppInterpreter_arm.S Tue Dec 20 13:49:11 2011 -0500
@@ -1318,6 +1318,7 @@
str tmp1, [ip, #JNIHANDLEBLOCK_TOP]
str r1, [r5, #4]
str r5, [r9, #THREAD_JAVA_SP]
+ mov r0, #0 @ deoptimized_frames = 0
ldmfd arm_sp!, {fast_regset, pc}
.fast_native_return_byte:
mov r0, r0, lsl #24
@@ -2083,10 +2084,20 @@
getstatic_volatile_dw:
DISPATCH_START 3
add r3, r3, lr
+#ifndef __ARM_ARCH_7A__
ldm r3, {r2, tmp2}
FullBarrier
DISPATCH_NEXT
PUSH r2, tmp2
+#else
+0: ldrexd tmp2, tmp1 , [r3]
+ strexd r2 , tmp2, tmp1, [r3]
+ teq r2, #0
+ bne 0b
+ FullBarrier
+ DISPATCH_NEXT
+ PUSH tmp2, tmp1
+#endif
DISPATCH_FINISH
getstatic_volatile_w:
DISPATCH_START 3
@@ -2125,11 +2136,20 @@
DISPATCH_FINISH
putstatic_volatile_dw:
DISPATCH_START 3
- add r2, r2, r3
- POP r3, tmp2
+ add ip, r2, r3
+ POP tmp1, tmp2
DISPATCH_NEXT
StoreStoreBarrier
- stm r2, {r3, tmp2}
+#ifndef __ARM_ARCH_7A__
+ stm ip, {tmp1, tmp2}
+#else
+ // Data in tmp1 & tmp2, address in ip, r2 & r3 scratch
+0: ldrexd r2, r3, [ip]
+ strexd r2, tmp2, tmp1, [ip]
+ teq r2, #0
+ bne 0b
+#endif
+ DISPATCH_NEXT
StoreLoadBarrier
DISPATCH_FINISH
putstatic_volatile_a:
diff -r d6cf8b242032 -r cf80d2049346 arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp
--- a/arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp Mon Dec 12 12:46:59 2011 -0500
+++ b/arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp Tue Dec 20 13:49:11 2011 -0500
@@ -392,7 +392,11 @@
#define H_HANDLE_EXCEPTION_NO_REGS 60
-unsigned handlers[61];
+#define H_SAFEPOINT 61
+
+#define H_LAST 62 // Not used
+
+unsigned handlers[H_LAST];
#define LEAF_STACK_SIZE 200
#define STACK_SPARE 40
@@ -651,6 +655,9 @@
#define IS_INT_SIZE_BASE_TYPE(c) (c=='B' || c=='C' || c=='F' || c=='I' || c=='S' || c=='Z')
#define IS_INT_SIZE_TYPE(c) (IS_INT_SIZE_BASE_TYPE(c) || c == 'L' || c == '[')
+void Thumb2_save_locals(Thumb2_Info *jinfo, unsigned stackdepth);
+void Thumb2_restore_locals(Thumb2_Info *jinfo, unsigned stackdepth);
+
static int method_stackchange(jbyte *base)
{
jbyte c;
@@ -2079,6 +2086,9 @@
#define T_STREX(dst, src, base, off) (0xe8400000 | ((base) << 16) | \
((src) << 12) | ((dst) << 8) | ((off >> 2)))
+#define T_LDREXD(dst1, dst2, base) (0xe8d0007f | ((base) << 16) | ((dst1) << 12) | (dst2 << 8))
+#define T_STREXD(dst, src1, src2, base) (0xe8c00070 | ((base) << 16) | ((src1) << 12) | (src2 << 8) | dst)
+
#define T_STM8(base, regset) (0xc000 | ((base) << 8) | (regset))
#define T_STM16(base, regset, st, wb) (0xe8000000 | ((st) << 23) | ((wb) << 21) | \
((base) << 16) | (regset))
@@ -2384,6 +2394,22 @@
J_Unimplemented();
}
+int ldrexd(CodeBuf *codebuf, Reg dst0, Reg dst1, Reg base)
+{
+ if (Thumb2) {
+ return out_16x2(codebuf, T_LDREXD(dst0, dst1, base));
+ }
+ J_Unimplemented();
+}
+
+int strexd(CodeBuf *codebuf, Reg dst, Reg src0, Reg src1, Reg base)
+{
+ if (Thumb2) {
+ return out_16x2(codebuf, T_STREXD(dst, src0, src1, base));
+ }
+ J_Unimplemented();
+}
+
int str_imm(CodeBuf *codebuf, Reg src, Reg base, int offset, int pre, int wb)
{
unsigned uoff;
@@ -4314,7 +4340,24 @@
void Thumb2_codegen(Thumb2_Info *jinfo, unsigned start);
-int Thumb2_Branch(Thumb2_Info *jinfo, unsigned bci, unsigned cond)
+// Insert code to poll the SafepointSynchronize state and call
+// Helper_SafePoint.
+void Thumb2_Safepoint(Thumb2_Info *jinfo, int stackdepth)
+{
+ int r_tmp = Thumb2_Tmp(jinfo, 0);
+ mov_imm(jinfo->codebuf, r_tmp, (u32)SafepointSynchronize::address_of_state());
+ ldr_imm(jinfo->codebuf, r_tmp, r_tmp, 0, 0, 0);
+ cmp_imm(jinfo->codebuf, r_tmp, SafepointSynchronize::_synchronizing);
+ {
+ unsigned loc = forward_16(jinfo->codebuf);
+ Thumb2_save_locals(jinfo, stackdepth);
+ bl(jinfo->codebuf, handlers[H_SAFEPOINT]);
+ Thumb2_restore_locals(jinfo, stackdepth);
+ bcc_patch(jinfo->codebuf, COND_NE, loc);
+ }
+}
+
+int Thumb2_Branch(Thumb2_Info *jinfo, unsigned bci, unsigned cond, int stackdepth)
{
int offset = GET_JAVA_S2(jinfo->code_base + bci + 1);
unsigned dest_taken = bci + offset;
@@ -4322,7 +4365,10 @@
unsigned loc;
if (jinfo->bc_stackinfo[dest_taken] & BC_COMPILED) {
- branch(jinfo->codebuf, cond, jinfo->bc_stackinfo[dest_taken] & ~BC_FLAGS_MASK);
+ loc = forward_16(jinfo->codebuf);
+ Thumb2_Safepoint(jinfo, stackdepth);
+ branch_uncond(jinfo->codebuf, jinfo->bc_stackinfo[dest_taken] & ~BC_FLAGS_MASK);
+ bcc_patch(jinfo->codebuf, NEG_COND(cond), loc);
return dest_not_taken;
}
loc = forward_32(jinfo->codebuf);
@@ -4332,13 +4378,14 @@
return -1;
}
-int Thumb2_Goto(Thumb2_Info *jinfo, unsigned bci, int offset, int len)
+int Thumb2_Goto(Thumb2_Info *jinfo, unsigned bci, int offset, int len, int stackdepth)
{
unsigned dest_taken = bci + offset;
unsigned dest_not_taken = bci + len;
unsigned loc;
if (jinfo->bc_stackinfo[dest_taken] & BC_COMPILED) {
+ Thumb2_Safepoint(jinfo, stackdepth);
branch_uncond(jinfo->codebuf, jinfo->bc_stackinfo[dest_taken] & ~BC_FLAGS_MASK);
return dest_not_taken;
}
@@ -4450,6 +4497,8 @@
Thumb2_Debug(jinfo, H_DEBUG_METHODEXIT);
// enter_leave(jinfo->codebuf, 0);
+ Thumb2_Safepoint(jinfo, 0);
+
// deoptimized_frames = 0
// FIXME: This should be done in the slow entry, but only three
// words are allocated there for the instructions.
@@ -4842,6 +4891,69 @@
H_D2F,
};
+// Generate code for a load of a jlong. If the operand is volatile,
+// generate a sequence of the form
+//
+// .Lsrc:
+// ldrexd r0, r1 , [src]
+// strexd r2 , r0, r1, [src]
+// cmp r2, #0
+// bne .Lsrc
+
+void Thumb2_load_long(Thumb2_Info *jinfo, Reg r_lo, Reg r_hi, Reg base,
+ int field_offset,
+ bool is_volatile = false)
+{
+ CodeBuf *codebuf = jinfo->codebuf;
+ if (is_volatile) {
+ Reg r_addr = base;
+ Reg tmp = Thumb2_Tmp(jinfo, (1<<r_lo) | (1<<r_hi) | (1<<base));
+ if (field_offset) {
+ r_addr = Thumb2_Tmp(jinfo, (1<<r_lo) | (1<<r_hi) | (1<<base) | (1<<tmp));
+ add_imm(jinfo->codebuf, r_addr, base, field_offset);
+ }
+ int loc = out_loc(codebuf);
+ ldrexd(codebuf, r_lo, r_hi, r_addr);
+ strexd(codebuf, tmp, r_lo, r_hi, r_addr);
+ cmp_imm(codebuf, tmp, 0);
+ branch(codebuf, COND_NE, loc);
+ } else {
+ ldrd_imm(codebuf, r_lo, r_hi, base, field_offset, 1, 0);
+ }
+}
+
+// Generate code for a load of a jlong. If the operand is volatile,
+// generate a sequence of the form
+//
+// .Ldst
+// ldrexd r2, r3, [dst]
+// strexd r2, r0, r1, [dst]
+// cmp r2, #0
+// bne .Ldst
+
+void Thumb2_store_long(Thumb2_Info *jinfo, Reg r_lo, Reg r_hi, Reg base,
+ int field_offset,
+ bool is_volatile = false)
+{
+ CodeBuf *codebuf = jinfo->codebuf;
+ if (is_volatile) {
+ Reg r_addr = base;
+ Reg tmp1 = Thumb2_Tmp(jinfo, (1<<r_lo) | (1<<r_hi) | (1<<base));
+ Reg tmp2 = Thumb2_Tmp(jinfo, (1<<r_lo) | (1<<r_hi) | (1<<base) | (1<<tmp1));
+ if (field_offset) {
+ r_addr = Thumb2_Tmp(jinfo, (1<<r_lo) | (1<<r_hi) | (1<<base) | (1<<tmp1) | (1<<tmp2));
+ add_imm(jinfo->codebuf, r_addr, base, field_offset);
+ }
+ int loc = out_loc(codebuf);
+ ldrexd(codebuf, tmp1, tmp2, r_addr);
+ strexd(codebuf, tmp1, r_lo, r_hi, r_addr);
+ cmp_imm(codebuf, tmp1, 0);
+ branch(codebuf, COND_NE, loc);
+ } else {
+ strd_imm(codebuf, r_lo, r_hi, base, field_offset, 1, 0);
+ }
+}
+
#define OPCODE2HANDLER(opc) (handlers[opcode2handler[(opc)-opc_idiv]])
extern "C" void _ZN18InterpreterRuntime18register_finalizerEP10JavaThreadP7oopDesc(void);
@@ -5657,7 +5769,8 @@
Thumb2_Spill(jinfo, 2, 0);
r_hi = PUSH(jstack, JSTACK_REG(jstack));
r_lo = PUSH(jstack, JSTACK_REG(jstack));
- ldrd_imm(jinfo->codebuf, r_lo, r_hi, r_obj, field_offset, 1, 0);
+ Thumb2_load_long(jinfo, r_lo, r_hi, r_obj, field_offset,
+ cache->is_volatile());
} else {
Reg r;
@@ -5718,13 +5831,15 @@
int field_offset = cache->f2();
if (tos_type == ltos || tos_type == dtos) {
- Reg r_lo, r_hi;
+ Reg r_lo, r_hi, r_addr;
Thumb2_Spill(jinfo, 2, 0);
r_hi = PUSH(jstack, JSTACK_REG(jstack));
r_lo = PUSH(jstack, JSTACK_REG(jstack));
+ r_addr = Thumb2_Tmp(jinfo, (1<<r_hi) | (1<<r_lo));
ldr_imm(jinfo->codebuf, r_lo, Ristate, ISTATE_CONSTANTS, 1, 0);
- ldr_imm(jinfo->codebuf, r_lo, r_lo, CP_OFFSET + (index << 4) + 4, 1, 0);
- ldrd_imm(jinfo->codebuf, r_lo, r_hi, r_lo, field_offset, 1, 0);
+ ldr_imm(jinfo->codebuf, r_addr, r_lo, CP_OFFSET + (index << 4) + 4, 1, 0);
+ Thumb2_load_long(jinfo, r_lo, r_hi, r_addr, field_offset,
+ cache->is_volatile());
} else {
Reg r;
Thumb2_Spill(jinfo, 1, 0);
@@ -5790,7 +5905,7 @@
r_lo = POP(jstack);
r_hi = POP(jstack);
r_obj = POP(jstack);
- strd_imm(jinfo->codebuf, r_lo, r_hi, r_obj, field_offset, 1, 0);
+ Thumb2_store_long(jinfo, r_lo, r_hi, r_obj, field_offset, cache->is_volatile());
} else {
Reg r;
Thumb2_Fill(jinfo, 2);
@@ -5860,7 +5975,7 @@
JASSERT(r_obj != r_lo && r_obj != r_hi, "corruption in putstatic");
ldr_imm(jinfo->codebuf, r_obj, Ristate, ISTATE_CONSTANTS, 1, 0);
ldr_imm(jinfo->codebuf, r_obj, r_obj, CP_OFFSET + (index << 4) + 4, 1, 0);
- strd_imm(jinfo->codebuf, r_lo, r_hi, r_obj, field_offset, 1, 0);
+ Thumb2_store_long(jinfo, r_lo, r_hi, r_obj, field_offset, cache->is_volatile());
} else {
Reg r;
Thumb2_Fill(jinfo, 1);
@@ -6176,7 +6291,7 @@
case opc_goto: {
int offset = GET_JAVA_S2(jinfo->code_base + bci + 1);
Thumb2_Flush(jinfo);
- bci = Thumb2_Goto(jinfo, bci, offset, len);
+ bci = Thumb2_Goto(jinfo, bci, offset, len, stackdepth);
len = 0;
break;
}
@@ -6184,7 +6299,7 @@
case opc_goto_w: {
int offset = GET_JAVA_U4(jinfo->code_base + bci + 1);
Thumb2_Flush(jinfo);
- bci = Thumb2_Goto(jinfo, bci, offset, len);
+ bci = Thumb2_Goto(jinfo, bci, offset, len, stackdepth);
len = 0;
break;
}
@@ -6204,7 +6319,7 @@
r = POP(jstack);
Thumb2_Flush(jinfo);
cmp_imm(jinfo->codebuf, r, 0);
- bci = Thumb2_Branch(jinfo, bci, cond);
+ bci = Thumb2_Branch(jinfo, bci, cond, stackdepth-1);
len = 0;
break;
}
@@ -6225,7 +6340,7 @@
r_lho = POP(jstack);
Thumb2_Flush(jinfo);
cmp_reg(jinfo->codebuf, r_lho, r_rho);
- bci = Thumb2_Branch(jinfo, bci, cond);
+ bci = Thumb2_Branch(jinfo, bci, cond, stackdepth-2);
len = 0;
break;
}
@@ -7150,6 +7265,7 @@
extern "C" void Helper_aputfield(void);
extern "C" void Helper_synchronized_enter(void);
extern "C" void Helper_synchronized_exit(void);
+extern "C" void Helper_SafePoint(void);
extern "C" void _ZN13SharedRuntime3f2iEf(void);
extern "C" void _ZN13SharedRuntime3f2lEf(void);
@@ -7620,6 +7736,22 @@
mov_imm(&codebuf, ARM_R3, (u32)Thumb2_Exit_To_Interpreter);
mov_reg(&codebuf, ARM_PC, ARM_R3);
+// H_SAFEPOINT
+ handlers[H_SAFEPOINT] = out_pos(&codebuf);
+ stm(&codebuf, (1<<ARM_LR), ARM_SP, PUSH_FD, 1);
+ mov_imm(&codebuf, ARM_IP, (u32)Helper_SafePoint);
+ mov_reg(&codebuf, ARM_R0, Rthread);
+ blx_reg(&codebuf, ARM_IP);
+ ldm(&codebuf, (1<<ARM_LR), ARM_SP, POP_FD, 1);
+ cmp_imm(&codebuf, ARM_R0, 0);
+ // The sequence here is delicate. We need to seet things up so that
+ // it looks as though Thumb2_Handle_Exception_NoRegs was called
+ // directly from a compiled method.
+ it(&codebuf, COND_EQ, IT_MASK_T);
+ mov_reg(&codebuf, ARM_PC, ARM_LR);
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