RFC: CACAO PR157 ARM memory barrier patch

Andrew Haley aph at redhat.com
Fri Mar 11 07:43:55 PST 2011

On 03/11/2011 03:40 PM, Xerxes Rånby wrote:
> On 2011-03-11 16:27, Andrew Haley wrote:
>> On 03/11/2011 03:12 PM, Xerxes Rånby wrote:
>>> On 2011-03-11 16:06, Matthias Klose wrote:
>>>> On 11.03.2011 14:59, Xerxes Rånby wrote:
>>>>> Hi
>>>>> The attached patch makes CACAO SMP safe on ARM by fixing
>>>>> CACAO PR157: ARM SMP Assertion thinlock failed.
>>>>> http://server.complang.tuwien.ac.at/cgi-bin/bugzilla/show_bug.cgi?id=157
>>>>> Ok to push to IcedTea6 HEAD and 1.10 branch?
>>>> please could you make this check depending on the compiler version used? As it
>>>> is not in 4.5.x fsf, the safe version to check would be 4.6.0.
>>>>   Matthias
>>> No, i dont think making this dependent on the compiler version would work.
>>> For what i know
>>> __asm__ __volatile__ ("" : : : "memory");
>>> do not generate any code and do not work as a memory barrier on ARM for any GCC version.
>> The gcc barrier is called __sync_synchronize().
> I will look into if I can make a follow up optimization patch for IcedTea6 HEAD
> that uses the GCC __sync_synchronize() memory barrier on GCC 4.5 and later in combination with ARMV7.
> The GCC __sync_synchronize() do emit an armv7+ dmb instruction directly
> that are faster than using the kernel helper on the latest ARM socs but only on GCC 4.5+ for what i have tested.

It's probably not worth doing.

In most cases you won't be able to use a barrier instruction, because GNU/Linux
(apart from Gentoo, I suppose) generally uses portable ARM binaries.  All that
a kernel running on a new ARM would do is place a couple of magic instructions
at 0xffff0fa0.  It would be pretty hard even to measure the performance difference,
I would have thought.


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