ARM: Mask shift counts
Andrew Haley
aph at redhat.com
Mon Nov 7 10:59:33 PST 2011
Some jtreg tests were failing because shifts were broken: they
do not AND the shift count with 0x1f. Fixed thusly.
Andrew.
011-11-07 Andrew Haley <aph at redhat.com>
* arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp (Thumb2_iOp): Mask
shift counts with 31.
(Thumb2_codegen): Mask double shift counts with 64.
diff -r 6f61af32cc26 arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp
--- a/arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp Wed Nov 02 16:20:25 2011 +0000
+++ b/arm_port/hotspot/src/cpu/zero/vm/thumb2.cpp Mon Nov 07 13:59:05 2011 -0500
@@ -4088,6 +4088,12 @@
Thumb2_Spill(jinfo, 1, 0);
r = JSTACK_REG(jstack);
PUSH(jstack, r);
+ switch (opc) {
+ case opc_ishl:
+ case opc_ishr:
+ and_imm(jinfo->codebuf, r_rho, r_rho, 31);
+ break;
+ }
dop_reg(jinfo->codebuf, dOps[opc-opc_iadd], r, r_lho, r_rho, 0, 0);
}
@@ -5157,6 +5163,7 @@
res_lo = PUSH(jstack, JSTACK_PREFER(jstack, ~((1<<lho_lo)|(1<<lho_hi))));
JASSERT(res_lo != lho_lo && res_lo != lho_hi, "Spill failed");
JASSERT(res_hi != lho_lo && res_hi != lho_hi, "Spill failed");
+ and_imm(jinfo->codebuf, shift, shift, 63);
and_imm(jinfo->codebuf, ARM_IP, shift, 31);
tst_imm(jinfo->codebuf, shift, 32);
loc1 = forward_16(jinfo->codebuf);
@@ -5186,6 +5193,7 @@
res_lo = PUSH(jstack, JSTACK_PREFER(jstack, ~((1<<lho_lo)|(1<<lho_hi))));
JASSERT(res_lo != lho_lo && res_lo != lho_hi, "Spill failed");
JASSERT(res_hi != lho_lo && res_hi != lho_hi, "Spill failed");
+ and_imm(jinfo->codebuf, shift, shift, 63);
and_imm(jinfo->codebuf, ARM_IP, shift, 31);
tst_imm(jinfo->codebuf, shift, 32);
loc1 = forward_16(jinfo->codebuf);
@@ -5215,6 +5223,7 @@
res_lo = PUSH(jstack, JSTACK_PREFER(jstack, ~((1<<lho_lo)|(1<<lho_hi))));
JASSERT(res_lo != lho_lo && res_lo != lho_hi, "Spill failed");
JASSERT(res_hi != lho_lo && res_hi != lho_hi, "Spill failed");
+ and_imm(jinfo->codebuf, shift, shift, 63);
and_imm(jinfo->codebuf, ARM_IP, shift, 31);
tst_imm(jinfo->codebuf, shift, 32);
loc1 = forward_16(jinfo->codebuf);
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