/hg/icedtea7-forest/hotspot: 11 new changesets
adinn at icedtea.classpath.org
adinn at icedtea.classpath.org
Mon Jun 1 10:53:29 UTC 2015
changeset 8e04e38c3fa8 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=8e04e38c3fa8
author: aph
date: Thu May 28 10:16:54 2015 -0400
8069593: Changes to JavaThread::_thread_state must use acquire and release
changeset 548020488783 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=548020488783
author: aph
date: Tue Mar 03 17:56:33 2015 +0000
8074349: AARCH64: C2 generates poor code for some byte and character stores
Summary: Use iRegIorL2I as src input for char and byte stores.
Reviewed-by: kvn
changeset c8f1b01693ba in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=c8f1b01693ba
author: aph
date: Thu May 28 10:25:15 2015 -0400
8075045: AARCH64: Stack banging should use store rather than load
Summary: Change stack bangs to use a store rather than a load
changeset 0bea9494c9cb in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=0bea9494c9cb
author: enevill
date: Wed May 27 15:03:26 2015 +0100
Add copyright to aarch64_ad.m4
changeset 63723278c978 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=63723278c978
author: aph
date: Fri May 29 09:31:52 2015 -0400
8075443: AARCH64: Missed L2I optimizations in C2
Summary: Use iRegIOrL2I for input operands whenever it makes sense.
changeset 84fa299120ce in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=84fa299120ce
author: aph
date: Fri May 29 09:45:44 2015 -0400
8075930: AARCH64: Use FP Register in C2
Summary: modify to allow C2 to allocate FP (R29) as a general register
changeset 137f1ed67e92 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=137f1ed67e92
author: aph
date: Fri May 29 10:38:35 2015 -0400
8076467: AARCH64: assertion fail with -XX:+UseG1GC
Summary: Don't call encoding unless bool is true.
changeset 3f4d11cdefe1 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=3f4d11cdefe1
author: enevill
date: Fri May 29 11:03:49 2015 -0400
8079203: AARCH64: Need to cater for different partner implementations
Summary: Parse /proc/cpuinfo to derive implementation specific info
changeset a74b6b4d0bde in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=a74b6b4d0bde
author: enevill
date: Wed May 27 15:40:40 2015 +0100
8080586: aarch64: hotspot test compiler/codegen/7184394/TestAESMain.java fails
Summary: Return correct length in generate_cipherBlockChaining_encryptAESCrypt
changeset 1795197a987f in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=1795197a987f
author: adinn
date: Fri May 29 11:20:12 2015 -0400
8075324: Costs of memory operands in aarch64.ad are inconsistent
Summary: Made cost of 'indOffI' consistent to the other memory operands.
changeset c96991560be1 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=c96991560be1
author: thartmann
date: Mon Mar 23 10:15:53 2015 +0100
8075136: Unnecessary sign extension for byte array access
Summary: Added C2 matching rules to remove unnecessary sign extension for byte array access.
Reviewed-by: roland, kvn, aph, adinn
diffstat:
src/cpu/aarch64/vm/aarch64.ad | 251 ++++++++++++--------
src/cpu/aarch64/vm/aarch64_ad.m4 | 51 +++-
src/cpu/aarch64/vm/assembler_aarch64.hpp | 2 +-
src/cpu/aarch64/vm/frame_aarch64.inline.hpp | 12 -
src/cpu/aarch64/vm/interp_masm_aarch64.hpp | 2 +
src/cpu/aarch64/vm/register_aarch64.hpp | 5 +-
src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp | 9 +-
src/cpu/aarch64/vm/stubGenerator_aarch64.cpp | 4 +-
src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp | 11 +-
src/cpu/aarch64/vm/vm_version_aarch64.cpp | 40 +++-
src/cpu/aarch64/vm/vm_version_aarch64.hpp | 34 ++
src/cpu/x86/vm/x86_64.ad | 61 ++++-
src/share/vm/runtime/thread.hpp | 2 +-
13 files changed, 341 insertions(+), 143 deletions(-)
diffs (truncated from 1325 to 500 lines):
diff -r c0ca0821c737 -r c96991560be1 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad Wed Apr 29 12:23:48 2015 -0700
+++ b/src/cpu/aarch64/vm/aarch64.ad Mon Mar 23 10:15:53 2015 +0100
@@ -447,7 +447,7 @@
R26
/* R27, */ // heapbase
/* R28, */ // thread
- /* R29, */ // fp
+ R29, // fp
/* R30, */ // lr
/* R31 */ // sp
);
@@ -481,7 +481,7 @@
R26, R26_H,
/* R27, R27_H, */ // heapbase
/* R28, R28_H, */ // thread
- /* R29, R29_H, */ // fp
+ R29, R29_H, // fp
/* R30, R30_H, */ // lr
/* R31, R31_H */ // sp
);
@@ -1728,7 +1728,7 @@
}
const RegMask Matcher::method_handle_invoke_SP_save_mask() {
- return RegMask();
+ return FP_REG_mask();
}
// helper for encoding java_to_runtime calls on sim
@@ -1811,6 +1811,8 @@
case INDINDEXSCALEDI2L:
case INDINDEXSCALEDOFFSETI2LN:
case INDINDEXSCALEDI2LN:
+ case INDINDEXOFFSETI2L:
+ case INDINDEXOFFSETI2LN:
scale = Address::sxtw(size);
break;
default:
@@ -2126,16 +2128,22 @@
enc_class aarch64_enc_stlrb(iRegI src, memory mem) %{
MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
rscratch1, stlrb);
+ if (VM_Version::cpu_cpuFeatures() & VM_Version::CPU_DMB_ATOMICS)
+ __ dmb(__ ISH);
%}
enc_class aarch64_enc_stlrh(iRegI src, memory mem) %{
MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
rscratch1, stlrh);
+ if (VM_Version::cpu_cpuFeatures() & VM_Version::CPU_DMB_ATOMICS)
+ __ dmb(__ ISH);
%}
enc_class aarch64_enc_stlrw(iRegI src, memory mem) %{
MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
rscratch1, stlrw);
+ if (VM_Version::cpu_cpuFeatures() & VM_Version::CPU_DMB_ATOMICS)
+ __ dmb(__ ISH);
%}
@@ -2226,6 +2234,8 @@
}
MOV_VOLATILE(src_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
rscratch1, stlr);
+ if (VM_Version::cpu_cpuFeatures() & VM_Version::CPU_DMB_ATOMICS)
+ __ dmb(__ ISH);
%}
enc_class aarch64_enc_fstlrs(vRegF src, memory mem) %{
@@ -2236,6 +2246,8 @@
}
MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
rscratch1, stlrw);
+ if (VM_Version::cpu_cpuFeatures() & VM_Version::CPU_DMB_ATOMICS)
+ __ dmb(__ ISH);
%}
enc_class aarch64_enc_fstlrd(vRegD src, memory mem) %{
@@ -2246,6 +2258,8 @@
}
MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
rscratch1, stlr);
+ if (VM_Version::cpu_cpuFeatures() & VM_Version::CPU_DMB_ATOMICS)
+ __ dmb(__ ISH);
%}
// synchronized read/update encodings
@@ -4285,6 +4299,20 @@
%}
%}
+operand indIndexOffsetI2L(iRegP reg, iRegI ireg, immLU12 off)
+%{
+ constraint(ALLOC_IN_RC(ptr_reg));
+ match(AddP (AddP reg (ConvI2L ireg)) off);
+ op_cost(INSN_COST);
+ format %{ "$reg, $ireg, $off I2L" %}
+ interface(MEMORY_INTER) %{
+ base($reg);
+ index($ireg);
+ scale(0x0);
+ disp($off);
+ %}
+%}
+
operand indIndexScaledOffsetI2L(iRegP reg, iRegI ireg, immIScale scale, immLU12 off)
%{
constraint(ALLOC_IN_RC(ptr_reg));
@@ -4345,7 +4373,7 @@
%{
constraint(ALLOC_IN_RC(ptr_reg));
match(AddP reg off);
- op_cost(INSN_COST);
+ op_cost(0);
format %{ "[$reg, $off]" %}
interface(MEMORY_INTER) %{
base($reg);
@@ -4415,6 +4443,21 @@
%}
%}
+operand indIndexOffsetI2LN(iRegN reg, iRegI ireg, immLU12 off)
+%{
+ predicate(Universe::narrow_oop_shift() == 0);
+ constraint(ALLOC_IN_RC(ptr_reg));
+ match(AddP (AddP (DecodeN reg) (ConvI2L ireg)) off);
+ op_cost(INSN_COST);
+ format %{ "$reg, $ireg, $off I2L\t# narrow" %}
+ interface(MEMORY_INTER) %{
+ base($reg);
+ index($ireg);
+ scale(0x0);
+ disp($off);
+ %}
+%}
+
operand indIndexScaledOffsetI2LN(iRegN reg, iRegI ireg, immIScale scale, immLU12 off)
%{
predicate(Universe::narrow_oop_shift() == 0);
@@ -4673,8 +4716,8 @@
// memory is used to define read/write location for load/store
// instruction defs. we can turn a memory op into an Address
-opclass memory(indirect, indIndexScaledOffsetI, indIndexScaledOffsetL, indIndexScaledOffsetI2L, indIndexScaled, indIndexScaledI2L, indIndex, indOffI, indOffL,
- indirectN, indIndexScaledOffsetIN, indIndexScaledOffsetLN, indIndexScaledOffsetI2LN, indIndexScaledN, indIndexScaledI2LN, indIndexN, indOffIN, indOffLN);
+opclass memory(indirect, indIndexScaledOffsetI, indIndexScaledOffsetL, indIndexOffsetI2L, indIndexScaledOffsetI2L, indIndexScaled, indIndexScaledI2L, indIndex, indOffI, indOffL,
+ indirectN, indIndexScaledOffsetIN, indIndexScaledOffsetLN, indIndexOffsetI2LN, indIndexScaledOffsetI2LN, indIndexScaledN, indIndexScaledI2LN, indIndexN, indOffIN, indOffLN);
// iRegIorL2I is used for src inputs in rules for 32 bit int (I)
// operations. it allows the src to be either an iRegI or a (ConvL2I
@@ -5616,7 +5659,7 @@
%}
// Store Byte
-instruct storeB(iRegI src, memory mem)
+instruct storeB(iRegIorL2I src, memory mem)
%{
match(Set mem (StoreB mem src));
@@ -5642,7 +5685,7 @@
%}
// Store Char/Short
-instruct storeC(iRegI src, memory mem)
+instruct storeC(iRegIorL2I src, memory mem)
%{
match(Set mem (StoreC mem src));
@@ -5943,7 +5986,7 @@
// ============================================================================
// Zero Count Instructions
-instruct countLeadingZerosI(iRegINoSp dst, iRegI src) %{
+instruct countLeadingZerosI(iRegINoSp dst, iRegIorL2I src) %{
match(Set dst (CountLeadingZerosI src));
ins_cost(INSN_COST);
@@ -5967,7 +6010,7 @@
ins_pipe( ialu_reg );
%}
-instruct countTrailingZerosI(iRegINoSp dst, iRegI src) %{
+instruct countTrailingZerosI(iRegINoSp dst, iRegIorL2I src) %{
match(Set dst (CountTrailingZerosI src));
ins_cost(INSN_COST * 2);
@@ -6539,7 +6582,7 @@
// which throws a ShouldNotHappen. So, we have to provide two flavours
// of each rule, one for a cmpOp and a second for a cmpOpU (sigh).
-instruct cmovI_reg_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegI src1, iRegI src2) %{
+instruct cmovI_reg_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
ins_cost(INSN_COST * 2);
@@ -6555,7 +6598,7 @@
ins_pipe(icond_reg_reg);
%}
-instruct cmovUI_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegI src1, iRegI src2) %{
+instruct cmovUI_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
ins_cost(INSN_COST * 2);
@@ -6580,7 +6623,7 @@
// we ought only to be able to cull one of these variants as the ideal
// transforms ought always to order the zero consistently (to left/right?)
-instruct cmovI_zero_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, iRegI src2) %{
+instruct cmovI_zero_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, iRegIorL2I src2) %{
match(Set dst (CMoveI (Binary cmp cr) (Binary zero src2)));
ins_cost(INSN_COST * 2);
@@ -6596,7 +6639,7 @@
ins_pipe(icond_reg);
%}
-instruct cmovUI_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, iRegI src2) %{
+instruct cmovUI_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, iRegIorL2I src2) %{
match(Set dst (CMoveI (Binary cmp cr) (Binary zero src2)));
ins_cost(INSN_COST * 2);
@@ -6612,7 +6655,7 @@
ins_pipe(icond_reg);
%}
-instruct cmovI_reg_zero(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegI src1, immI0 zero) %{
+instruct cmovI_reg_zero(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegIorL2I src1, immI0 zero) %{
match(Set dst (CMoveI (Binary cmp cr) (Binary src1 zero)));
ins_cost(INSN_COST * 2);
@@ -6628,7 +6671,7 @@
ins_pipe(icond_reg);
%}
-instruct cmovUI_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegI src1, immI0 zero) %{
+instruct cmovUI_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegIorL2I src1, immI0 zero) %{
match(Set dst (CMoveI (Binary cmp cr) (Binary src1 zero)));
ins_cost(INSN_COST * 2);
@@ -7080,7 +7123,7 @@
ins_pipe(ialu_reg_reg);
%}
-instruct addI_reg_imm(iRegINoSp dst, iRegI src1, immIAddSub src2) %{
+instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAddSub src2) %{
match(Set dst (AddI src1 src2));
ins_cost(INSN_COST);
@@ -7127,7 +7170,7 @@
instruct addP_reg_reg_ext(iRegPNoSp dst, iRegP src1, iRegIorL2I src2) %{
match(Set dst (AddP src1 (ConvI2L src2)));
- ins_cost(INSN_COST);
+ ins_cost(1.9 * INSN_COST);
format %{ "add $dst, $src1, $src2, sxtw\t# ptr" %}
ins_encode %{
@@ -7473,7 +7516,7 @@
ins_pipe(idiv_reg_reg);
%}
-instruct signExtract(iRegINoSp dst, iRegI src, immI_31 div1, immI_31 div2) %{
+instruct signExtract(iRegINoSp dst, iRegIorL2I src, immI_31 div1, immI_31 div2) %{
match(Set dst (URShiftI (RShiftI src div1) div2));
ins_cost(INSN_COST);
format %{ "lsrw $dst, $src, $div1" %}
@@ -7483,7 +7526,7 @@
ins_pipe(ialu_reg_shift);
%}
-instruct div2Round(iRegINoSp dst, iRegI src, immI_31 div1, immI_31 div2) %{
+instruct div2Round(iRegINoSp dst, iRegIorL2I src, immI_31 div1, immI_31 div2) %{
match(Set dst (AddI src (URShiftI (RShiftI src div1) div2)));
ins_cost(INSN_COST);
format %{ "addw $dst, $src, LSR $div1" %}
@@ -7793,7 +7836,7 @@
ins_pipe(ialu_reg);
%}
instruct regI_not_reg(iRegINoSp dst,
- iRegI src1, immI_M1 m1,
+ iRegIorL2I src1, immI_M1 m1,
rFlagsReg cr) %{
match(Set dst (XorI src1 m1));
ins_cost(INSN_COST);
@@ -7810,10 +7853,27 @@
%}
instruct AndI_reg_not_reg(iRegINoSp dst,
- iRegI src1, iRegI src2, immI_M1 m1,
+ iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1,
rFlagsReg cr) %{
match(Set dst (AndI src1 (XorI src2 m1)));
ins_cost(INSN_COST);
+ format %{ "bicw $dst, $src1, $src2" %}
+
+ ins_encode %{
+ __ bicw(as_Register($dst$$reg),
+ as_Register($src1$$reg),
+ as_Register($src2$$reg),
+ Assembler::LSL, 0);
+ %}
+
+ ins_pipe(ialu_reg_reg);
+%}
+
+instruct AndL_reg_not_reg(iRegLNoSp dst,
+ iRegL src1, iRegL src2, immL_M1 m1,
+ rFlagsReg cr) %{
+ match(Set dst (AndL src1 (XorL src2 m1)));
+ ins_cost(INSN_COST);
format %{ "bic $dst, $src1, $src2" %}
ins_encode %{
@@ -7826,15 +7886,15 @@
ins_pipe(ialu_reg_reg);
%}
-instruct AndL_reg_not_reg(iRegLNoSp dst,
- iRegL src1, iRegL src2, immL_M1 m1,
+instruct OrI_reg_not_reg(iRegINoSp dst,
+ iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1,
rFlagsReg cr) %{
- match(Set dst (AndL src1 (XorL src2 m1)));
- ins_cost(INSN_COST);
- format %{ "bic $dst, $src1, $src2" %}
-
- ins_encode %{
- __ bic(as_Register($dst$$reg),
+ match(Set dst (OrI src1 (XorI src2 m1)));
+ ins_cost(INSN_COST);
+ format %{ "ornw $dst, $src1, $src2" %}
+
+ ins_encode %{
+ __ ornw(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL, 0);
@@ -7843,10 +7903,10 @@
ins_pipe(ialu_reg_reg);
%}
-instruct OrI_reg_not_reg(iRegINoSp dst,
- iRegI src1, iRegI src2, immI_M1 m1,
+instruct OrL_reg_not_reg(iRegLNoSp dst,
+ iRegL src1, iRegL src2, immL_M1 m1,
rFlagsReg cr) %{
- match(Set dst (OrI src1 (XorI src2 m1)));
+ match(Set dst (OrL src1 (XorL src2 m1)));
ins_cost(INSN_COST);
format %{ "orn $dst, $src1, $src2" %}
@@ -7860,15 +7920,15 @@
ins_pipe(ialu_reg_reg);
%}
-instruct OrL_reg_not_reg(iRegLNoSp dst,
- iRegL src1, iRegL src2, immL_M1 m1,
+instruct XorI_reg_not_reg(iRegINoSp dst,
+ iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1,
rFlagsReg cr) %{
- match(Set dst (OrL src1 (XorL src2 m1)));
- ins_cost(INSN_COST);
- format %{ "orn $dst, $src1, $src2" %}
-
- ins_encode %{
- __ orn(as_Register($dst$$reg),
+ match(Set dst (XorI m1 (XorI src2 src1)));
+ ins_cost(INSN_COST);
+ format %{ "eonw $dst, $src1, $src2" %}
+
+ ins_encode %{
+ __ eonw(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL, 0);
@@ -7877,10 +7937,10 @@
ins_pipe(ialu_reg_reg);
%}
-instruct XorI_reg_not_reg(iRegINoSp dst,
- iRegI src1, iRegI src2, immI_M1 m1,
+instruct XorL_reg_not_reg(iRegLNoSp dst,
+ iRegL src1, iRegL src2, immL_M1 m1,
rFlagsReg cr) %{
- match(Set dst (XorI m1 (XorI src2 src1)));
+ match(Set dst (XorL m1 (XorL src2 src1)));
ins_cost(INSN_COST);
format %{ "eon $dst, $src1, $src2" %}
@@ -7894,25 +7954,8 @@
ins_pipe(ialu_reg_reg);
%}
-instruct XorL_reg_not_reg(iRegLNoSp dst,
- iRegL src1, iRegL src2, immL_M1 m1,
- rFlagsReg cr) %{
- match(Set dst (XorL m1 (XorL src2 src1)));
- ins_cost(INSN_COST);
- format %{ "eon $dst, $src1, $src2" %}
-
- ins_encode %{
- __ eon(as_Register($dst$$reg),
- as_Register($src1$$reg),
- as_Register($src2$$reg),
- Assembler::LSL, 0);
- %}
-
- ins_pipe(ialu_reg_reg);
-%}
-
instruct AndI_reg_URShift_not_reg(iRegINoSp dst,
- iRegI src1, iRegI src2,
+ iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
match(Set dst (AndI src1 (XorI(URShiftI src2 src3) src4)));
ins_cost(1.9 * INSN_COST);
@@ -7948,7 +7991,7 @@
%}
instruct AndI_reg_RShift_not_reg(iRegINoSp dst,
- iRegI src1, iRegI src2,
+ iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
match(Set dst (AndI src1 (XorI(RShiftI src2 src3) src4)));
ins_cost(1.9 * INSN_COST);
@@ -7984,7 +8027,7 @@
%}
instruct AndI_reg_LShift_not_reg(iRegINoSp dst,
- iRegI src1, iRegI src2,
+ iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
match(Set dst (AndI src1 (XorI(LShiftI src2 src3) src4)));
ins_cost(1.9 * INSN_COST);
@@ -8020,7 +8063,7 @@
%}
instruct XorI_reg_URShift_not_reg(iRegINoSp dst,
- iRegI src1, iRegI src2,
+ iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
match(Set dst (XorI src4 (XorI(URShiftI src2 src3) src1)));
ins_cost(1.9 * INSN_COST);
@@ -8056,7 +8099,7 @@
%}
instruct XorI_reg_RShift_not_reg(iRegINoSp dst,
- iRegI src1, iRegI src2,
+ iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
match(Set dst (XorI src4 (XorI(RShiftI src2 src3) src1)));
ins_cost(1.9 * INSN_COST);
@@ -8092,7 +8135,7 @@
%}
instruct XorI_reg_LShift_not_reg(iRegINoSp dst,
- iRegI src1, iRegI src2,
+ iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
match(Set dst (XorI src4 (XorI(LShiftI src2 src3) src1)));
ins_cost(1.9 * INSN_COST);
@@ -8128,7 +8171,7 @@
%}
instruct OrI_reg_URShift_not_reg(iRegINoSp dst,
- iRegI src1, iRegI src2,
+ iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
match(Set dst (OrI src1 (XorI(URShiftI src2 src3) src4)));
ins_cost(1.9 * INSN_COST);
@@ -8164,7 +8207,7 @@
%}
instruct OrI_reg_RShift_not_reg(iRegINoSp dst,
- iRegI src1, iRegI src2,
+ iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
match(Set dst (OrI src1 (XorI(RShiftI src2 src3) src4)));
ins_cost(1.9 * INSN_COST);
@@ -8200,7 +8243,7 @@
%}
instruct OrI_reg_LShift_not_reg(iRegINoSp dst,
- iRegI src1, iRegI src2,
+ iRegIorL2I src1, iRegIorL2I src2,
immI src3, immI_M1 src4, rFlagsReg cr) %{
match(Set dst (OrI src1 (XorI(LShiftI src2 src3) src4)));
ins_cost(1.9 * INSN_COST);
@@ -8236,7 +8279,7 @@
%}
instruct AndI_reg_URShift_reg(iRegINoSp dst,
- iRegI src1, iRegI src2,
+ iRegIorL2I src1, iRegIorL2I src2,
immI src3, rFlagsReg cr) %{
match(Set dst (AndI src1 (URShiftI src2 src3)));
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