/hg/icedtea7-forest/hotspot: 8 new changesets
enevill at icedtea.classpath.org
enevill at icedtea.classpath.org
Wed Nov 4 10:35:11 UTC 2015
changeset 37ec298f263d in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=37ec298f263d
author: enevill
date: Wed May 27 09:02:08 2015 +0000
8081289: aarch64: add support for RewriteFrequentPairs in interpreter
Summary: Add support for RewriteFrequentPairs
Reviewed-by: roland
Contributed-by: alexander.alexeev at caviumnetworks.com
changeset 25ce0dcaaebe in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=25ce0dcaaebe
author: enevill
date: Thu Jul 16 14:16:44 2015 +0000
8131483: aarch64: illegal stlxr instructions
Summary: Do not generate stlxX with Ws == Xn
Reviewed-by: kvn, aph
changeset 027348ed6e01 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=027348ed6e01
author: enevill
date: Tue Aug 18 12:40:22 2015 +0000
8133352: aarch64: generates constrained unpredictable instructions
Summary: Fix generation of unpredictable STXR Rs, Rt, [Rn] with Rs == Rt
Reviewed-by: kvn, aph, adinn
changeset 7b194a9b9fa1 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=7b194a9b9fa1
author: enevill
date: Thu Aug 20 09:40:08 2015 +0000
8133842: aarch64: C2 generates illegal instructions with int shifts >=32
Summary: Fix logical operatations combined with shifts >= 32
Reviewed-by: duke
changeset 065c4ead59c3 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=065c4ead59c3
author: adinn
date: Wed Aug 26 17:13:59 2015 +0100
8134322: AArch64: Fix several errors in C2 biased locking implementation
Summary: Several errors in C2 biased locking require fixing
Reviewed-by: kvn
Contributed-by: hui.shi at linaro.org
changeset 9739ea27122a in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=9739ea27122a
author: enevill
date: Wed Sep 16 13:50:57 2015 +0000
8136615: aarch64: elide DecodeN when followed by CmpP 0
Summary: remove DecodeN when comparing a narrow oop with 0
Reviewed-by: kvn, adinn
changeset ad277cc2ef09 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=ad277cc2ef09
author: aph
date: Wed Sep 30 13:23:46 2015 +0000
8138641: Disable C2 peephole by default for aarch64
Reviewed-by: roland
Contributed-by: felix.yang at linaro.org
changeset 75d1c4168925 in /hg/icedtea7-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea7-forest/hotspot?cmd=changeset;node=75d1c4168925
author: aph
date: Tue Sep 29 17:01:37 2015 +0000
8138575: Improve generated code for profile counters
Reviewed-by: kvn
diffstat:
src/cpu/aarch64/vm/aarch64.ad | 106 ++++++++++++--------
src/cpu/aarch64/vm/aarch64_ad.m4 | 4 +-
src/cpu/aarch64/vm/assembler_aarch64.cpp | 95 ++++++++++++------
src/cpu/aarch64/vm/assembler_aarch64.hpp | 22 +--
src/cpu/aarch64/vm/c2_globals_aarch64.hpp | 2 +-
src/cpu/aarch64/vm/globals_aarch64.hpp | 2 +-
src/cpu/aarch64/vm/interp_masm_aarch64.cpp | 7 +-
src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp | 3 +-
src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp | 7 +-
src/cpu/aarch64/vm/templateTable_aarch64.cpp | 107 +++++++++++++++++++-
10 files changed, 248 insertions(+), 107 deletions(-)
diffs (truncated from 963 to 500 lines):
diff -r 43c066bdfc9f -r 75d1c4168925 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad Thu Aug 06 00:08:57 2015 -0700
+++ b/src/cpu/aarch64/vm/aarch64.ad Tue Sep 29 17:01:37 2015 +0000
@@ -2930,12 +2930,12 @@
return;
}
- if (UseBiasedLocking) {
- __ biased_locking_enter(disp_hdr, oop, box, tmp, true, cont);
+ if (UseBiasedLocking && !UseOptoBiasInlining) {
+ __ biased_locking_enter(box, oop, disp_hdr, tmp, true, cont);
}
// Handle existing monitor
- if (EmitSync & 0x02) {
+ if ((EmitSync & 0x02) == 0) {
// we can use AArch64's bit test and branch here but
// markoopDesc does not define a bit index just the bit value
// so assert in case the bit pos changes
@@ -3075,7 +3075,7 @@
return;
}
- if (UseBiasedLocking) {
+ if (UseBiasedLocking && !UseOptoBiasInlining) {
__ biased_locking_exit(oop, tmp, cont);
}
@@ -7966,7 +7966,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8002,7 +8002,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8038,7 +8038,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8074,7 +8074,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8110,7 +8110,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8146,7 +8146,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8182,7 +8182,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8218,7 +8218,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8254,7 +8254,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8291,7 +8291,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8329,7 +8329,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8367,7 +8367,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8405,7 +8405,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8443,7 +8443,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8481,7 +8481,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8519,7 +8519,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8557,7 +8557,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8595,7 +8595,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8633,7 +8633,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8671,7 +8671,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8709,7 +8709,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8747,7 +8747,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8785,7 +8785,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8823,7 +8823,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8866,8 +8866,8 @@
int s = 63 - lshift;
int r = (rshift - lshift) & 63;
__ sbfm(as_Register($dst$$reg),
- as_Register($src$$reg),
- r, s);
+ as_Register($src$$reg),
+ r, s);
%}
ins_pipe(ialu_reg_shift);
@@ -8889,8 +8889,8 @@
int s = 31 - lshift;
int r = (rshift - lshift) & 31;
__ sbfmw(as_Register($dst$$reg),
- as_Register($src$$reg),
- r, s);
+ as_Register($src$$reg),
+ r, s);
%}
ins_pipe(ialu_reg_shift);
@@ -8912,8 +8912,8 @@
int s = 63 - lshift;
int r = (rshift - lshift) & 63;
__ ubfm(as_Register($dst$$reg),
- as_Register($src$$reg),
- r, s);
+ as_Register($src$$reg),
+ r, s);
%}
ins_pipe(ialu_reg_shift);
@@ -8935,8 +8935,8 @@
int s = 31 - lshift;
int r = (rshift - lshift) & 31;
__ ubfmw(as_Register($dst$$reg),
- as_Register($src$$reg),
- r, s);
+ as_Register($src$$reg),
+ r, s);
%}
ins_pipe(ialu_reg_shift);
@@ -8954,7 +8954,7 @@
long mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfxw(as_Register($dst$$reg),
- as_Register($src$$reg), rshift, width);
+ as_Register($src$$reg), rshift, width);
%}
ins_pipe(ialu_reg_shift);
%}
@@ -8969,7 +8969,7 @@
long mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfx(as_Register($dst$$reg),
- as_Register($src$$reg), rshift, width);
+ as_Register($src$$reg), rshift, width);
%}
ins_pipe(ialu_reg_shift);
%}
@@ -8987,7 +8987,7 @@
long mask = $mask$$constant;
int width = exact_log2(mask+1);
__ ubfx(as_Register($dst$$reg),
- as_Register($src$$reg), rshift, width);
+ as_Register($src$$reg), rshift, width);
%}
ins_pipe(ialu_reg_shift);
%}
@@ -9066,7 +9066,7 @@
ins_encode %{
__ subw(rscratch1, zr, as_Register($shift$$reg));
__ rorv(as_Register($dst$$reg), as_Register($src$$reg),
- rscratch1);
+ rscratch1);
%}
ins_pipe(ialu_reg_reg_vshift);
%}
@@ -9082,7 +9082,7 @@
ins_encode %{
__ subw(rscratch1, zr, as_Register($shift$$reg));
__ rorvw(as_Register($dst$$reg), as_Register($src$$reg),
- rscratch1);
+ rscratch1);
%}
ins_pipe(ialu_reg_reg_vshift);
%}
@@ -9133,7 +9133,7 @@
ins_cost(INSN_COST);
ins_encode %{
__ rorv(as_Register($dst$$reg), as_Register($src$$reg),
- as_Register($shift$$reg));
+ as_Register($shift$$reg));
%}
ins_pipe(ialu_reg_reg_vshift);
%}
@@ -9148,7 +9148,7 @@
ins_cost(INSN_COST);
ins_encode %{
__ rorvw(as_Register($dst$$reg), as_Register($src$$reg),
- as_Register($shift$$reg));
+ as_Register($shift$$reg));
%}
ins_pipe(ialu_reg_reg_vshift);
%}
@@ -9442,7 +9442,6 @@
// END This section of the file is automatically generated. Do not edit --------------
-
// ============================================================================
// Floating Point Arithmetic Instructions
@@ -11051,6 +11050,25 @@
ins_pipe(pipe_cmp_branch);
%}
+instruct cmpP_narrowOop_imm0_branch(cmpOp cmp, iRegN oop, immP0 zero, label labl, rFlagsReg cr) %{
+ match(If cmp (CmpP (DecodeN oop) zero));
+ predicate(n->in(1)->as_Bool()->_test._test == BoolTest::ne
+ || n->in(1)->as_Bool()->_test._test == BoolTest::eq);
+ effect(USE labl);
+
+ ins_cost(BRANCH_COST);
+ format %{ "cb$cmp $oop, $labl" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
+ if (cond == Assembler::EQ)
+ __ cbzw($oop$$Register, *L);
+ else
+ __ cbnzw($oop$$Register, *L);
+ %}
+ ins_pipe(pipe_cmp_branch);
+%}
+
// Conditional Far Branch
// Conditional Far Branch Unsigned
// TODO: fixme
diff -r 43c066bdfc9f -r 75d1c4168925 src/cpu/aarch64/vm/aarch64_ad.m4
--- a/src/cpu/aarch64/vm/aarch64_ad.m4 Thu Aug 06 00:08:57 2015 -0700
+++ b/src/cpu/aarch64/vm/aarch64_ad.m4 Tue Sep 29 17:01:37 2015 +0000
@@ -42,7 +42,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::$5,
- $src3$$constant & 0x3f);
+ $src3$$constant & ifelse($1,I,0x1f,0x3f));
%}
ins_pipe(ialu_reg_reg_shift);
@@ -87,7 +87,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::$5,
- $src3$$constant & 0x3f);
+ $src3$$constant & ifelse($1,I,0x1f,0x3f));
%}
ins_pipe(ialu_reg_reg_shift);
diff -r 43c066bdfc9f -r 75d1c4168925 src/cpu/aarch64/vm/assembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.cpp Thu Aug 06 00:08:57 2015 -0700
+++ b/src/cpu/aarch64/vm/assembler_aarch64.cpp Tue Sep 29 17:01:37 2015 +0000
@@ -281,14 +281,14 @@
// LoadStoreExclusiveOp
__ stxr(r20, r21, r2); // stxr w20, x21, [x2]
- __ stlxr(r7, r29, r7); // stlxr w7, x29, [x7]
+ __ stlxr(r5, r29, r7); // stlxr w5, x29, [x7]
__ ldxr(r5, r16); // ldxr x5, [x16]
__ ldaxr(r27, r29); // ldaxr x27, [x29]
__ stlr(r0, r29); // stlr x0, [x29]
__ ldar(r21, r28); // ldar x21, [x28]
// LoadStoreExclusiveOp
- __ stxrw(r24, r24, r7); // stxr w24, w24, [x7]
+ __ stxrw(r21, r24, r7); // stxr w21, w24, [x7]
__ stlxrw(r21, r26, r28); // stlxr w21, w26, [x28]
__ ldxrw(r21, r6); // ldxr w21, [x6]
__ ldaxrw(r15, r30); // ldaxr w15, [x30]
@@ -315,11 +315,11 @@
__ ldxp(r8, r2, r19); // ldxp x8, x2, [x19]
__ ldaxp(r7, r19, r14); // ldaxp x7, x19, [x14]
__ stxp(r8, r27, r28, r5); // stxp w8, x27, x28, [x5]
- __ stlxp(r6, r8, r14, r6); // stlxp w6, x8, x14, [x6]
+ __ stlxp(r5, r8, r14, r6); // stlxp w5, x8, x14, [x6]
// LoadStoreExclusiveOp
__ ldxpw(r25, r4, r22); // ldxp w25, w4, [x22]
- __ ldaxpw(r14, r14, r15); // ldaxp w14, w14, [x15]
+ __ ldaxpw(r13, r14, r15); // ldaxp w13, w14, [x15]
__ stxpw(r20, r26, r8, r10); // stxp w20, w26, w8, [x10]
__ stlxpw(r23, r18, r18, r18); // stlxp w23, w18, w18, [x18]
@@ -788,12 +788,12 @@
24c: d61f0040 br x2
250: d63f00a0 blr x5
254: c8147c55 stxr w20, x21, [x2]
- 258: c807fcfd stlxr w7, x29, [x7]
+ 258: c805fcfd stlxr w5, x29, [x7]
25c: c85f7e05 ldxr x5, [x16]
260: c85fffbb ldaxr x27, [x29]
264: c89fffa0 stlr x0, [x29]
268: c8dfff95 ldar x21, [x28]
- 26c: 88187cf8 stxr w24, w24, [x7]
+ 26c: 88157cf8 stxr w21, w24, [x7]
270: 8815ff9a stlxr w21, w26, [x28]
274: 885f7cd5 ldxr w21, [x6]
278: 885fffcf ldaxr w15, [x30]
@@ -814,9 +814,9 @@
2b4: c87f0a68 ldxp x8, x2, [x19]
2b8: c87fcdc7 ldaxp x7, x19, [x14]
2bc: c82870bb stxp w8, x27, x28, [x5]
- 2c0: c826b8c8 stlxp w6, x8, x14, [x6]
+ 2c0: c825b8c8 stlxp w5, x8, x14, [x6]
2c4: 887f12d9 ldxp w25, w4, [x22]
- 2c8: 887fb9ee ldaxp w14, w14, [x15]
+ 2c8: 887fb9ed ldaxp w13, w14, [x15]
2cc: 8834215a stxp w20, w26, w8, [x10]
2d0: 8837ca52 stlxp w23, w18, w18, [x18]
2d4: f806317e str x30, [x11,#99]
@@ -1104,14 +1104,14 @@
0xd4063721, 0xd4035082, 0xd400bfe3, 0xd4282fc0,
0xd444c320, 0xd503201f, 0xd69f03e0, 0xd6bf03e0,
0xd5033fdf, 0xd5033f9f, 0xd5033abf, 0xd61f0040,
- 0xd63f00a0, 0xc8147c55, 0xc807fcfd, 0xc85f7e05,
- 0xc85fffbb, 0xc89fffa0, 0xc8dfff95, 0x88187cf8,
+ 0xd63f00a0, 0xc8147c55, 0xc805fcfd, 0xc85f7e05,
+ 0xc85fffbb, 0xc89fffa0, 0xc8dfff95, 0x88157cf8,
0x8815ff9a, 0x885f7cd5, 0x885fffcf, 0x889ffc73,
0x88dffc56, 0x48127c0f, 0x480bff85, 0x485f7cdd,
0x485ffcf2, 0x489fff99, 0x48dffe62, 0x080a7c3e,
0x0814fed5, 0x085f7c59, 0x085ffcb8, 0x089ffc70,
0x08dfffb6, 0xc87f0a68, 0xc87fcdc7, 0xc82870bb,
- 0xc826b8c8, 0x887f12d9, 0x887fb9ee, 0x8834215a,
+ 0xc825b8c8, 0x887f12d9, 0x887fb9ed, 0x8834215a,
0x8837ca52, 0xf806317e, 0xb81b3337, 0x39000dc2,
0x78005149, 0xf84391f4, 0xb85b220c, 0x385fd356,
0x785d127e, 0x389f4149, 0x79801e3c, 0x79c014a3,
@@ -1878,11 +1878,7 @@
if (PrintBiasedLockingStatistics && counters == NULL)
counters = BiasedLocking::counters();
- bool need_tmp_reg = false;
- if (tmp_reg == noreg) {
- tmp_reg = rscratch2;
- }
- assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1);
+ assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, rscratch1, rscratch2, noreg);
assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
@@ -1912,7 +1908,7 @@
if (counters != NULL) {
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