/hg/icedtea8-forest/hotspot: 36 new changesets
andrew at icedtea.classpath.org
andrew at icedtea.classpath.org
Thu Jul 14 03:00:22 UTC 2016
changeset 7c89f7f3f2c5 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=7c89f7f3f2c5
author: thartmann
date: Mon Jul 11 04:03:50 2016 +0100
8159244, PR3074: Partially initialized string object created by C2's string concat optimization may escape
Summary: Emit release barrier after String creation to prevent partially initialized object from escaping.
Reviewed-by: kvn
changeset b54e7d073b31 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=b54e7d073b31
author: roland
date: Tue Apr 19 19:52:39 2016 -0700
8154537, PR3078: AArch64: some integer rotate instructions are never emitted
Reviewed-by: aph, adinn, kvn
changeset 699d2d234e67 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=699d2d234e67
author: roland
date: Mon Apr 25 15:14:02 2016 +0200
8155015, PR3078: Aarch64: bad assert in spill generation code
Reviewed-by: thartmann
changeset e9af35def13b in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=e9af35def13b
author: roland
date: Thu Apr 28 15:24:17 2016 +0200
8155612, PR3078: Aarch64: vector nodes need to support misaligned offset
Summary: Add support for misaligned offsets.
Reviewed-by: aph
changeset f2320f55ec5a in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=f2320f55ec5a
author: zmajo
date: Fri Apr 29 14:32:19 2016 +0200
8155653, PR3078: TestVectorUnalignedOffset.java not pushed with 8155612
Summary: Add missing test.
Reviewed-by: aph, adinn
changeset c79658b66387 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=c79658b66387
author: aph
date: Tue Apr 26 14:38:39 2016 +0000
8155100, PR3078: AArch64: Relax alignment requirement for byte_map_base
Reviewed-by: roland
changeset 699420added1 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=699420added1
author: aph
date: Wed Apr 20 11:14:10 2016 +0000
8154739, PR3078: AArch64: TemplateTable::fast_xaccess loads in wrong mode
Reviewed-by: roland
changeset 7e281c566425 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=7e281c566425
author: aph
date: Mon May 23 15:39:13 2016 +0000
8150045, PR3078: arraycopy causes segfaults in SATB during garbage collection
Reviewed-by: roland
changeset 70cd739f16b4 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=70cd739f16b4
author: enevill
date: Thu Feb 04 16:24:28 2016 +0000
8148783, PR3078: aarch64: SEGV running SpecJBB2013
Summary: Fix calculation of offset for adrp
Reviewed-by: aph
changeset d7e4e50d3116 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=d7e4e50d3116
author: enevill
date: Wed Feb 03 11:34:12 2016 +0000
8148948, PR3078: aarch64: generate_copy_longs calls align() incorrectly
Summary: Fix alignments
Reviewed-by: aph
changeset 8835ded0d2d9 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=8835ded0d2d9
author: enevill
date: Mon Feb 08 14:14:35 2016 +0000
8149365, PR3078: aarch64: memory copy does not prefetch on backwards copy
Summary: Implement prefetch on backwards copies
Reviewed-by: aph
changeset e69bb50a32d1 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=e69bb50a32d1
author: hshi
date: Fri Feb 05 03:55:51 2016 -0800
8149080, PR3078: AArch64: Recognise disjoint array copy in stub code
Summary: Detect array copy can use fwd copy by checking (dest-src) above_same (copy_size)
Reviewed-by: aph
changeset 0943cf8920d9 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=0943cf8920d9
author: enevill
date: Sat Feb 20 15:11:42 2016 +0000
8150082, PR3078: aarch64: optimise small array copy
Reviewed-by: aph
changeset 9fa0039dd555 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=9fa0039dd555
author: enevill
date: Sat Feb 20 15:15:35 2016 +0000
8150313, PR3078: aarch64: optimise array copy using SIMD instructions
Reviewed-by: aph
changeset 7d0f315c1abc in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=7d0f315c1abc
author: enevill
date: Tue Mar 08 14:39:50 2016 +0000
8150394, PR3078: aarch64: add support for 8.1 LSE CAS instructions
Reviewed-by: aph
Contributed-by: ananth.jasty at caviumnetworks.com, edward.nevill at linaro.org
changeset 522f95506bdb in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=522f95506bdb
author: enevill
date: Thu Mar 10 14:53:09 2016 +0000
8151502, PR3078: optimize pd_disjoint_words and pd_conjoint_words
Summary: optimize copy routines using inline assembler
Reviewed-by: aph
changeset 2a24fd4a3b59 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=2a24fd4a3b59
author: enevill
date: Tue Mar 29 10:07:54 2016 +0000
8151775, PR3078: aarch64: add support for 8.1 LSE atomic operations
Reviewed-by: aph
changeset 6d7233008f42 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=6d7233008f42
author: fyang
date: Wed Mar 23 18:00:46 2016 +0800
8152537, PR3078: aarch64: Make use of CBZ and CBNZ when comparing unsigned values with zero.
Summary: aarch64: c2 make use of CBZ and CBNZ when comparing unsigned values with zero.
Reviewed-by: aph
changeset d43f14cfce87 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=d43f14cfce87
author: fyang
date: Fri Feb 19 17:12:14 2016 +0800
8150229, PR3078: aarch64: pipeline class for several instructions is not set correctly
Summary: aarch64: c2 fix pipeline class for several instructions.
Reviewed-by: aph
Contributed-by: felix.yang at linaro.org
changeset 180e94d83244 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=180e94d83244
author: fyang
date: Thu Feb 18 21:53:24 2016 +0800
8149907, PR3078: aarch64: use load/store pair instructions in call_stub
Summary: aarch64: make use of load/store pair instructions in call_stub to save space
Reviewed-by: aph
Contributed-by: felix.yang at linaro.org
changeset 4a4f1bb0c82b in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=4a4f1bb0c82b
author: fyang
date: Wed Feb 17 20:19:24 2016 +0800
8150038, PR3078: aarch64: make use of CBZ and CBNZ when comparing narrow pointer with zero
Summary: aarch64: c2 make use of CBZ and CBNZ when comparing narrow pointer with zero
Reviewed-by: aph
Contributed-by: felix.yang at linaro.org
changeset e39d2820eedf in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=e39d2820eedf
author: fyang
date: Wed Jan 27 12:20:53 2016 +0800
8148328, PR3078: aarch64: redundant lsr instructions in stub code.
Summary: avoid redundant lsr instructions in jbyte_arraycopy and jbyte_disjoint_arraycopy.
Reviewed-by: aph
Contributed-by: felix.yang at linaro.org
changeset 693a61c1ba77 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=693a61c1ba77
author: enevill
date: Thu Apr 07 22:36:16 2016 +0000
8153797, PR3078: aarch64: Add Arrays.fill stub code
Reviewed-by: aph
Contributed-by: long.chen at linaro.org
changeset 2329ec94e550 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=2329ec94e550
author: fyang
date: Sat Mar 05 22:22:37 2016 +0800
8151340, PR3078: aarch64: prefetch the destination word for write prior to ldxr/stxr loops.
Summary: aarch64: add prefetch for write prior to ldxr/stxr loops.
Reviewed-by: aph
Contributed-by: felix.yang at linaro.org
changeset 6a252d870435 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=6a252d870435
author: fyang
date: Tue Apr 12 11:53:44 2016 +0800
8153713, PR3078: aarch64: improve short array clearing using store pair
Summary: aarch64: generate store pair instruction to clear short arrays
Reviewed-by: aph
changeset 8b05ecddace0 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=8b05ecddace0
author: enevill
date: Thu Apr 28 13:26:29 2016 +0000
8155617, PR3078: aarch64: ClearArray does not use DC ZVA
Summary: Implement block zero using DC ZVA
Reviewed-by: aph
Contributed-by: long.chen at linaro.org, edward.nevill at gmail.com
changeset f2ee814c7937 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=f2ee814c7937
author: enevill
date: Wed May 25 13:30:07 2016 +0000
8157841, PR3078: aarch64: prefetch ignores cache line size
Summary: fix prefetch to take account of cache line size
Reviewed-by: aph
Contributed-by: stuart.monteith at linaro.org, edward.nevill at linaro.org
changeset e6f5563d859b in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=e6f5563d859b
author: fyang
date: Fri May 27 20:38:38 2016 +0800
8157906, PR3078: aarch64: some more integer rotate instructions are never emitted
Summary: fix wrong definition of source operand of left rotate instructions
Reviewed-by: aph
Contributed-by: teng.lu at linaro.org
changeset 1c7b01e0f6fb in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=1c7b01e0f6fb
author: aph
date: Mon Dec 14 15:53:48 2015 +0000
8145320, PR3078: Create unsafe_arraycopy and generic_arraycopy for AArch64
Reviewed-by: kvn
changeset e9ac89cbafe9 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=e9ac89cbafe9
author: fyang
date: Mon Mar 28 21:21:41 2016 +0800
8152840, PR3078: aarch64: improve _unsafe_arraycopy stub routine
Summary: aarch64: improve StubRoutines::_unsafe_arraycopy stub routine
Reviewed-by: aph
changeset 847893b9f498 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=847893b9f498
author: fyang
date: Fri May 27 01:02:16 2016 +0800
8156731, PR3078: aarch64: java/util/Arrays/Correct.java fails due to _generic_arraycopy stub routine
Summary: fix address calculation considering compressed oops _generic_arraycopy stub routine
Reviewed-by: aph
changeset df7be90ca2ab in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=df7be90ca2ab
author: enevill
date: Wed Jun 08 12:45:29 2016 +0000
8159052, PR3078: aarch64: optimise unaligned copies in pd_disjoint_words and pd_conjoint_words
Reviewed-by: aph
changeset c4920d708cee in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=c4920d708cee
author: enevill
date: Tue Jun 07 10:17:28 2016 +0000
8158913, PR3078: aarch64: SEGV running Spark terasort
Summary: Use signed instead of unsigned test for end of loop in gen_write_ref_array_post_barrier
Reviewed-by: aph
Contributed-by: felix.yang at linaro.org
changeset ea6933324a7a in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=ea6933324a7a
author: enevill
date: Fri Jun 24 10:35:41 2016 +0000
8159063, PR3078: aarch64: optimise unaligned array copy long
Reviewed-by: aph
Contributed-by: edward.nevill at gmail.com, adinn at redhat.com
changeset 2363c25f4802 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=2363c25f4802
author: andrew
date: Thu Jul 14 02:29:53 2016 +0100
PR3078: Cleanup remaining differences from aarch64/jdk8u tree
changeset bb14c5df7088 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=bb14c5df7088
author: andrew
date: Thu Jul 14 04:02:40 2016 +0100
Added tag icedtea-3.1.0pre03 for changeset ea6933324a7a
diffstat:
.hgtags | 1 +
make/defs.make | 2 +-
make/linux/makefiles/defs.make | 18 +-
src/cpu/aarch64/vm/aarch64.ad | 381 ++-
src/cpu/aarch64/vm/assembler_aarch64.hpp | 122 +-
src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp | 116 +-
src/cpu/aarch64/vm/globals_aarch64.hpp | 18 +-
src/cpu/aarch64/vm/macroAssembler_aarch64.cpp | 350 ++-
src/cpu/aarch64/vm/macroAssembler_aarch64.hpp | 49 +-
src/cpu/aarch64/vm/register_aarch64.hpp | 3 +
src/cpu/aarch64/vm/stubGenerator_aarch64.cpp | 1239 ++++++++-
src/cpu/aarch64/vm/stubRoutines_aarch64.cpp | 1 +
src/cpu/aarch64/vm/stubRoutines_aarch64.hpp | 7 +
src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp | 23 +-
src/cpu/aarch64/vm/templateTable_aarch64.cpp | 4 +-
src/cpu/aarch64/vm/vm_version_aarch64.cpp | 86 +-
src/cpu/aarch64/vm/vm_version_aarch64.hpp | 27 +-
src/os_cpu/linux_aarch64/vm/atomic_linux_aarch64.inline.hpp | 93 +-
src/os_cpu/linux_aarch64/vm/copy_linux_aarch64.inline.hpp | 182 +-
src/os_cpu/linux_aarch64/vm/copy_linux_aarch64.s | 411 +++
src/share/vm/opto/stringopts.cpp | 8 +-
src/share/vm/runtime/sharedRuntime.cpp | 5 -
test/compiler/codegen/IntRotateWithImmediate.java | 24 +-
test/compiler/stringopts/TestStringObjectInitialization.java | 78 +
test/compiler/vectorization/TestVectorUnalignedOffset.java | 55 +
25 files changed, 2827 insertions(+), 476 deletions(-)
diffs (truncated from 4534 to 500 lines):
diff -r 4b40867e627d -r bb14c5df7088 .hgtags
--- a/.hgtags Fri Jun 17 11:31:24 2016 +0200
+++ b/.hgtags Thu Jul 14 04:02:40 2016 +0100
@@ -872,3 +872,4 @@
f3e1e734e2d29101a9537ddeb71ecad413fcd352 jdk8u92-b13
cbd30c92ef7a62846124e28b35aaf668621b1105 icedtea-3.1.0pre01
76eca5cf31500ecb1d1807685729a7ea5c3780e7 icedtea-3.1.0pre02
+ea6933324a7a52379d7f1e18e7525fd619079865 icedtea-3.1.0pre03
diff -r 4b40867e627d -r bb14c5df7088 make/defs.make
--- a/make/defs.make Fri Jun 17 11:31:24 2016 +0200
+++ b/make/defs.make Thu Jul 14 04:02:40 2016 +0100
@@ -285,7 +285,7 @@
# Use uname output for SRCARCH, but deal with platform differences. If ARCH
# is not explicitly listed below, it is treated as x86.
- SRCARCH ?= $(ARCH/$(filter sparc sparc64 ia64 amd64 x86_64 aarch64 ppc ppc64 zero,$(ARCH)))
+ SRCARCH ?= $(ARCH/$(filter sparc sparc64 ia64 amd64 x86_64 ppc ppc64 zero aarch64,$(ARCH)))
ARCH/ = x86
ARCH/sparc = sparc
ARCH/sparc64= sparc
diff -r 4b40867e627d -r bb14c5df7088 make/linux/makefiles/defs.make
--- a/make/linux/makefiles/defs.make Fri Jun 17 11:31:24 2016 +0200
+++ b/make/linux/makefiles/defs.make Thu Jul 14 04:02:40 2016 +0100
@@ -98,15 +98,6 @@
HS_ARCH = x86
endif
-# AARCH64
-ifeq ($(ARCH), aarch64)
- ARCH_DATA_MODEL = 64
- MAKE_ARGS += LP64=1
- PLATFORM = linux-aarch64
- VM_PLATFORM = linux_aarch64
- HS_ARCH = aarch64
-endif
-
# PPC
# Notice: after 8046471 ARCH will be 'ppc' for top-level ppc64 builds but
# 'ppc64' for HotSpot-only ppc64 builds. Need to detect both variants here!
@@ -123,6 +114,15 @@
HS_ARCH = ppc
endif
+# AARCH64
+ifeq ($(ARCH), aarch64)
+ ARCH_DATA_MODEL = 64
+ MAKE_ARGS += LP64=1
+ PLATFORM = linux-aarch64
+ VM_PLATFORM = linux_aarch64
+ HS_ARCH = aarch64
+endif
+
# On 32 bit linux we build server and client, on 64 bit just server.
ifeq ($(JVM_VARIANTS),)
ifeq ($(ARCH_DATA_MODEL), 32)
diff -r 4b40867e627d -r bb14c5df7088 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad Fri Jun 17 11:31:24 2016 +0200
+++ b/src/cpu/aarch64/vm/aarch64.ad Thu Jul 14 04:02:40 2016 +0100
@@ -3140,7 +3140,7 @@
assert((src_lo_rc != rc_int && dst_lo_rc != rc_int), "sanity");
if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
// stack->stack
- assert((src_offset & 7) && (dst_offset & 7), "unaligned stack offset");
+ assert((src_offset & 7) == 0 && (dst_offset & 7) == 0, "unaligned stack offset");
if (ireg == Op_VecD) {
__ unspill(rscratch1, true, src_offset);
__ spill(rscratch1, true, dst_offset);
@@ -3470,7 +3470,7 @@
const bool Matcher::init_array_count_is_in_bytes = false;
// Threshold size for cleararray.
-const int Matcher::init_array_short_size = 18 * BytesPerLong;
+const int Matcher::init_array_short_size = 4 * BytesPerLong;
// Use conditional move (CMOVL)
const int Matcher::long_cmove_cost() {
@@ -4253,14 +4253,14 @@
MacroAssembler _masm(&cbuf);
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
- &Assembler::ldxr, &MacroAssembler::cmp, &Assembler::stlxr);
+ Assembler::xword, /*acquire*/ false, /*release*/ true);
%}
enc_class aarch64_enc_cmpxchgw(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
MacroAssembler _masm(&cbuf);
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
- &Assembler::ldxrw, &MacroAssembler::cmpw, &Assembler::stlxrw);
+ Assembler::word, /*acquire*/ false, /*release*/ true);
%}
@@ -4272,14 +4272,14 @@
MacroAssembler _masm(&cbuf);
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
- &Assembler::ldaxr, &MacroAssembler::cmp, &Assembler::stlxr);
+ Assembler::xword, /*acquire*/ true, /*release*/ true);
%}
enc_class aarch64_enc_cmpxchgw_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
MacroAssembler _masm(&cbuf);
guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
__ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
- &Assembler::ldaxrw, &MacroAssembler::cmpw, &Assembler::stlxrw);
+ Assembler::word, /*acquire*/ true, /*release*/ true);
%}
// auxiliary used for CompareAndSwapX to set result register
@@ -4349,55 +4349,6 @@
}
%}
- enc_class aarch64_enc_clear_array_reg_reg(iRegL_R11 cnt, iRegP_R10 base) %{
- MacroAssembler _masm(&cbuf);
- Register cnt_reg = as_Register($cnt$$reg);
- Register base_reg = as_Register($base$$reg);
- // base is word aligned
- // cnt is count of words
-
- Label loop;
- Label entry;
-
-// Algorithm:
-//
-// scratch1 = cnt & 7;
-// cnt -= scratch1;
-// p += scratch1;
-// switch (scratch1) {
-// do {
-// cnt -= 8;
-// p[-8] = 0;
-// case 7:
-// p[-7] = 0;
-// case 6:
-// p[-6] = 0;
-// // ...
-// case 1:
-// p[-1] = 0;
-// case 0:
-// p += 8;
-// } while (cnt);
-// }
-
- const int unroll = 8; // Number of str(zr) instructions we'll unroll
-
- __ andr(rscratch1, cnt_reg, unroll - 1); // tmp1 = cnt % unroll
- __ sub(cnt_reg, cnt_reg, rscratch1); // cnt -= unroll
- // base_reg always points to the end of the region we're about to zero
- __ add(base_reg, base_reg, rscratch1, Assembler::LSL, exact_log2(wordSize));
- __ adr(rscratch2, entry);
- __ sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 2);
- __ br(rscratch2);
- __ bind(loop);
- __ sub(cnt_reg, cnt_reg, unroll);
- for (int i = -unroll; i < 0; i++)
- __ str(zr, Address(base_reg, i * wordSize));
- __ bind(entry);
- __ add(base_reg, base_reg, unroll * wordSize);
- __ cbnz(cnt_reg, loop);
- %}
-
/// mov envcodings
enc_class aarch64_enc_movw_imm(iRegI dst, immI src) %{
@@ -4847,8 +4798,15 @@
// Compare object markOop with mark and if equal exchange scratch1
// with object markOop.
- {
+ if (UseLSE) {
+ __ mov(tmp, disp_hdr);
+ __ casal(Assembler::xword, tmp, box, oop);
+ __ cmp(tmp, disp_hdr);
+ __ br(Assembler::EQ, cont);
+ } else {
Label retry_load;
+ if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_STXR_PREFETCH))
+ __ prfm(Address(oop), PSTL1STRM);
__ bind(retry_load);
__ ldaxr(tmp, oop);
__ cmp(tmp, disp_hdr);
@@ -4897,8 +4855,14 @@
__ add(tmp, disp_hdr, (ObjectMonitor::owner_offset_in_bytes()-markOopDesc::monitor_value));
__ mov(disp_hdr, zr);
- {
+ if (UseLSE) {
+ __ mov(rscratch1, disp_hdr);
+ __ casal(Assembler::xword, rscratch1, rthread, tmp);
+ __ cmp(rscratch1, disp_hdr);
+ } else {
Label retry_load, fail;
+ if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_STXR_PREFETCH))
+ __ prfm(Address(tmp), PSTL1STRM);
__ bind(retry_load);
__ ldaxr(rscratch1, tmp);
__ cmp(disp_hdr, rscratch1);
@@ -4986,8 +4950,14 @@
// see the stack address of the basicLock in the markOop of the
// object.
- {
+ if (UseLSE) {
+ __ mov(tmp, box);
+ __ casl(Assembler::xword, tmp, disp_hdr, oop);
+ __ cmp(tmp, box);
+ } else {
Label retry_load;
+ if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_STXR_PREFETCH))
+ __ prfm(Address(oop), PSTL1STRM);
__ bind(retry_load);
__ ldxr(tmp, oop);
__ cmp(box, tmp);
@@ -5506,6 +5476,36 @@
interface(CONST_INTER);
%}
+operand immIOffset4()
+%{
+ predicate(Address::offset_ok_for_immed(n->get_int(), 2));
+ match(ConI);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
+operand immIOffset8()
+%{
+ predicate(Address::offset_ok_for_immed(n->get_int(), 3));
+ match(ConI);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
+operand immIOffset16()
+%{
+ predicate(Address::offset_ok_for_immed(n->get_int(), 4));
+ match(ConI);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
operand immLoffset()
%{
predicate(Address::offset_ok_for_immed(n->get_long()));
@@ -5516,6 +5516,36 @@
interface(CONST_INTER);
%}
+operand immLoffset4()
+%{
+ predicate(Address::offset_ok_for_immed(n->get_long(), 2));
+ match(ConL);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
+operand immLoffset8()
+%{
+ predicate(Address::offset_ok_for_immed(n->get_long(), 3));
+ match(ConL);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
+operand immLoffset16()
+%{
+ predicate(Address::offset_ok_for_immed(n->get_long(), 4));
+ match(ConL);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
// 32 bit integer valid for add sub immediate
operand immIAddSub()
%{
@@ -6350,7 +6380,7 @@
%}
%}
-operand indOffL(iRegP reg, immLoffset off)
+operand indOffI4(iRegP reg, immIOffset4 off)
%{
constraint(ALLOC_IN_RC(ptr_reg));
match(AddP reg off);
@@ -6364,6 +6394,89 @@
%}
%}
+operand indOffI8(iRegP reg, immIOffset8 off)
+%{
+ constraint(ALLOC_IN_RC(ptr_reg));
+ match(AddP reg off);
+ op_cost(0);
+ format %{ "[$reg, $off]" %}
+ interface(MEMORY_INTER) %{
+ base($reg);
+ index(0xffffffff);
+ scale(0x0);
+ disp($off);
+ %}
+%}
+
+operand indOffI16(iRegP reg, immIOffset16 off)
+%{
+ constraint(ALLOC_IN_RC(ptr_reg));
+ match(AddP reg off);
+ op_cost(0);
+ format %{ "[$reg, $off]" %}
+ interface(MEMORY_INTER) %{
+ base($reg);
+ index(0xffffffff);
+ scale(0x0);
+ disp($off);
+ %}
+%}
+
+operand indOffL(iRegP reg, immLoffset off)
+%{
+ constraint(ALLOC_IN_RC(ptr_reg));
+ match(AddP reg off);
+ op_cost(0);
+ format %{ "[$reg, $off]" %}
+ interface(MEMORY_INTER) %{
+ base($reg);
+ index(0xffffffff);
+ scale(0x0);
+ disp($off);
+ %}
+%}
+
+operand indOffL4(iRegP reg, immLoffset4 off)
+%{
+ constraint(ALLOC_IN_RC(ptr_reg));
+ match(AddP reg off);
+ op_cost(0);
+ format %{ "[$reg, $off]" %}
+ interface(MEMORY_INTER) %{
+ base($reg);
+ index(0xffffffff);
+ scale(0x0);
+ disp($off);
+ %}
+%}
+
+operand indOffL8(iRegP reg, immLoffset8 off)
+%{
+ constraint(ALLOC_IN_RC(ptr_reg));
+ match(AddP reg off);
+ op_cost(0);
+ format %{ "[$reg, $off]" %}
+ interface(MEMORY_INTER) %{
+ base($reg);
+ index(0xffffffff);
+ scale(0x0);
+ disp($off);
+ %}
+%}
+
+operand indOffL16(iRegP reg, immLoffset16 off)
+%{
+ constraint(ALLOC_IN_RC(ptr_reg));
+ match(AddP reg off);
+ op_cost(0);
+ format %{ "[$reg, $off]" %}
+ interface(MEMORY_INTER) %{
+ base($reg);
+ index(0xffffffff);
+ scale(0x0);
+ disp($off);
+ %}
+%}
operand indirectN(iRegN reg)
%{
@@ -6676,7 +6789,9 @@
interface(REG_INTER)
%}
-opclass vmem(indirect, indIndex, indOffI, indOffL);
+opclass vmem4(indirect, indIndex, indOffI4, indOffL4);
+opclass vmem8(indirect, indIndex, indOffI8, indOffL8);
+opclass vmem16(indirect, indIndex, indOffI16, indOffL16);
//----------OPERAND CLASSES----------------------------------------------------
// Operand Classes are groups of operands that are used as to simplify
@@ -7210,7 +7325,7 @@
NEON_FP : S3;
%}
-pipe_class vload_reg_mem64(vecD dst, vmem mem)
+pipe_class vload_reg_mem64(vecD dst, vmem8 mem)
%{
single_instruction;
dst : S5(write);
@@ -7219,7 +7334,7 @@
NEON_FP : S3;
%}
-pipe_class vload_reg_mem128(vecX dst, vmem mem)
+pipe_class vload_reg_mem128(vecX dst, vmem16 mem)
%{
single_instruction;
dst : S5(write);
@@ -7228,7 +7343,7 @@
NEON_FP : S3;
%}
-pipe_class vstore_reg_mem64(vecD src, vmem mem)
+pipe_class vstore_reg_mem64(vecD src, vmem8 mem)
%{
single_instruction;
mem : ISS(read);
@@ -7237,7 +7352,7 @@
NEON_FP : S3;
%}
-pipe_class vstore_reg_mem128(vecD src, vmem mem)
+pipe_class vstore_reg_mem128(vecD src, vmem16 mem)
%{
single_instruction;
mem : ISS(read);
@@ -12189,21 +12304,21 @@
%}
%}
-instruct rolI_rReg_Var_C_32(iRegLNoSp dst, iRegL src, iRegI shift, immI_32 c_32, rFlagsReg cr)
+instruct rolI_rReg_Var_C_32(iRegINoSp dst, iRegI src, iRegI shift, immI_32 c_32, rFlagsReg cr)
%{
match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c_32 shift))));
expand %{
- rolL_rReg(dst, src, shift, cr);
- %}
-%}
-
-instruct rolI_rReg_Var_C0(iRegLNoSp dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
+ rolI_rReg(dst, src, shift, cr);
+ %}
+%}
+
+instruct rolI_rReg_Var_C0(iRegINoSp dst, iRegI src, iRegI shift, immI0 c0, rFlagsReg cr)
%{
match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c0 shift))));
expand %{
- rolL_rReg(dst, src, shift, cr);
+ rolI_rReg(dst, src, shift, cr);
%}
%}
@@ -12255,21 +12370,21 @@
%}
%}
-instruct rorI_rReg_Var_C_32(iRegLNoSp dst, iRegL src, iRegI shift, immI_32 c_32, rFlagsReg cr)
+instruct rorI_rReg_Var_C_32(iRegINoSp dst, iRegI src, iRegI shift, immI_32 c_32, rFlagsReg cr)
%{
match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c_32 shift))));
expand %{
- rorL_rReg(dst, src, shift, cr);
- %}
-%}
-
-instruct rorI_rReg_Var_C0(iRegLNoSp dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
+ rorI_rReg(dst, src, shift, cr);
+ %}
+%}
+
+instruct rorI_rReg_Var_C0(iRegINoSp dst, iRegI src, iRegI shift, immI0 c0, rFlagsReg cr)
%{
match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c0 shift))));
expand %{
- rorL_rReg(dst, src, shift, cr);
+ rorI_rReg(dst, src, shift, cr);
%}
%}
@@ -13426,7 +13541,7 @@
__ fmovs($dst$$Register, as_FloatRegister($src$$reg));
%}
- ins_pipe(pipe_class_memory);
+ ins_pipe(fp_f2i);
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