/hg/release/icedtea7-forest-2.6/hotspot: 23 new changesets
andrew at icedtea.classpath.org
andrew at icedtea.classpath.org
Thu Jul 21 16:02:14 UTC 2016
changeset 8eef7715af0b in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=8eef7715af0b
author: minqi
date: Wed Jun 01 19:31:26 2016 +0100
2178143, PR2958: JVM crashes if the number of bound CPUs changed during runtime
Summary: Supply a new flag -XX:+AssumeMP to workaround the problem. With the flag is turned on, assume VM run on MP platform so is_MP() will return true that sync calls will not skip away.
Reviewed-by: dholmes, acorn, dcubed, jmasa
Contributed-by: yumin.qi at oracle.com
changeset 4f8cbd54a9c6 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=4f8cbd54a9c6
author: simonis
date: Wed Jul 20 03:15:59 2016 +0100
8158260, PR2992, RH1341258: PPC64: unaligned Unsafe.getInt can lead to the generation of illegal instructions
Summary: Adjust instruction generation. Includes portions of 8026049 for test case.
Reviewed-by: goetz
Contributed-by: gromero at linux.vnet.ibm.com, horii at jp.ibm.com
changeset 0ba5a39aca0a in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=0ba5a39aca0a
author: kvn
date: Tue Jul 19 21:22:43 2016 +0100
6934604, PR3075: enable parts of EliminateAutoBox by default
Summary: Resurrected autobox elimination code and enabled part of it by default.
Reviewed-by: roland, twisti
changeset 22008ee271ed in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=22008ee271ed
author: kvn
date: Mon May 13 14:36:39 2013 -0700
8014286, PR3075: failed java/lang/Math/DivModTests.java after 6934604 changes
Summary: Corrected escape state for the result of boxing method. Added force inlining executed boxing methods.
Reviewed-by: twisti
changeset 3321b4f21fba in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=3321b4f21fba
author: kvn
date: Tue Jul 02 10:30:49 2013 -0700
8019247, PR3075: SIGSEGV in compiled method c8e.e.t_.getArray(Ljava/lang/Class;)[Ljava/lang/Object
Summary: Undo recent changes (and add more comments) in Ideal_allocation().
Reviewed-by: roland
changeset 725a97b380d2 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=725a97b380d2
author: drchase
date: Tue Jul 19 23:13:01 2016 +0100
8014959, PR3075: assert(Compile::current()->live_nodes() < (uint)MaxNodeLimit) failed: Live Node limit exceeded limit
Summary: Insert extra checks and bailouts for too many nodes
Reviewed-by: kvn
changeset b40cadf40ab7 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=b40cadf40ab7
author: thartmann
date: Tue Jul 19 23:59:47 2016 +0100
8159244, PR3075: Partially initialized string object created by C2's string concat optimization may escape
Summary: Emit release barrier after String creation to prevent partially initialized object from escaping.
Reviewed-by: kvn
changeset 4b50705cd316 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=4b50705cd316
author: andrew
date: Fri Jul 08 01:58:45 2016 +0100
8151841, PR3098: Build needs additional flags to compile with GCC 6
Summary: C++ standard needs to be explicitly set and some optimisations turned off to build on GCC 6
Reviewed-by: erikj, dholmes, kbarrett
changeset da12b61bf5a2 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=da12b61bf5a2
author: roland
date: Tue Apr 19 19:52:39 2016 -0700
8154537, PR3100: AArch64: some integer rotate instructions are never emitted
Reviewed-by: aph, adinn, kvn
changeset b96466d40a92 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=b96466d40a92
author: aph
date: Wed Apr 20 11:14:10 2016 +0000
8154739, PR3100: AArch64: TemplateTable::fast_xaccess loads in wrong mode
Reviewed-by: roland
changeset bb1818a74170 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=bb1818a74170
author: aph
date: Mon May 23 15:39:13 2016 +0000
8150045, PR3100: arraycopy causes segfaults in SATB during garbage collection
Reviewed-by: roland
changeset 30fa347a47e6 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=30fa347a47e6
author: enevill
date: Thu Feb 04 16:24:28 2016 +0000
8148783, PR3100: aarch64: SEGV running SpecJBB2013
Summary: Fix calculation of offset for adrp
Reviewed-by: aph
changeset e174f34bc41c in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=e174f34bc41c
author: enevill
date: Wed Feb 03 11:34:12 2016 +0000
8148948, PR3100: aarch64: generate_copy_longs calls align() incorrectly
Summary: Fix alignments
Reviewed-by: aph
changeset f3f52408a4d2 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=f3f52408a4d2
author: fyang
date: Wed Jan 27 12:20:53 2016 +0800
8148328, PR3100: aarch64: redundant lsr instructions in stub code.
Summary: avoid redundant lsr instructions in jbyte_arraycopy and jbyte_disjoint_arraycopy.
Reviewed-by: aph
Contributed-by: felix.yang at linaro.org
changeset b4a17ff67e26 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=b4a17ff67e26
author: fyang
date: Fri May 27 20:38:38 2016 +0800
8157906, PR3100: aarch64: some more integer rotate instructions are never emitted
Summary: fix wrong definition of source operand of left rotate instructions
Reviewed-by: aph
Contributed-by: teng.lu at linaro.org
changeset 0437c24fbd58 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=0437c24fbd58
author: andrew
date: Wed Jul 20 04:00:44 2016 +0100
Added tag icedtea-2.6.7pre01 for changeset b4a17ff67e26
changeset e34324d73cd5 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=e34324d73cd5
author: andrew
date: Fri Jul 08 01:58:45 2016 +0100
8151841: Build needs additional flags to compile with GCC 6
Summary: C++ standard needs to be explicitly set and some optimisations turned off to build on GCC 6
Reviewed-by: erikj, dholmes, kbarrett
changeset bd3158bf90dc in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=bd3158bf90dc
author: vkempik
date: Fri Jul 08 15:06:04 2016 +0100
8152479: Coded byte streams
Reviewed-by: hseigel
changeset 9877542f0855 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=9877542f0855
author: shshahma
date: Wed May 11 12:03:46 2016 -0400
8155981: Bolster bytecode verification
Reviewed-by: acorn, jdn
Contributed-by: harold.seigel at oracle.com
changeset 165b97219811 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=165b97219811
author: iklam
date: Fri Jul 15 06:04:31 2016 +0100
8150752: Share Class Data
Reviewed-by: acorn, hseigel, mschoene
changeset 14d0f4da4a74 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=14d0f4da4a74
author: amurillo
date: Fri Jul 15 17:05:18 2016 +0100
8079410: Hotspot version to share the same update and build version from JDK
Reviewed-by: dholmes, dcubed
changeset 9efa3fae3c27 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=9efa3fae3c27
author: andrew
date: Wed Jul 20 04:05:08 2016 +0100
Added tag jdk7u111-b00 for changeset 14d0f4da4a74
changeset e98d35509eaf in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=e98d35509eaf
author: andrew
date: Wed Jul 20 05:26:25 2016 +0100
Merge jdk7u111-b00
diffstat:
.hgtags | 2 +
make/defs.make | 12 +
make/hotspot_version | 2 +-
make/linux/makefiles/gcc.make | 7 +
src/cpu/aarch64/vm/aarch64.ad | 28 +-
src/cpu/aarch64/vm/assembler_aarch64.cpp | 16 +-
src/cpu/aarch64/vm/globals_aarch64.hpp | 4 -
src/cpu/aarch64/vm/stubGenerator_aarch64.cpp | 39 +-
src/cpu/aarch64/vm/templateTable_aarch64.cpp | 4 +-
src/cpu/aarch64/vm/vm_version_aarch64.cpp | 8 +-
src/cpu/ppc/vm/ppc.ad | 4 +-
src/cpu/ppc/vm/vm_version_ppc.cpp | 9 +-
src/cpu/sparc/vm/vm_version_sparc.cpp | 9 +-
src/cpu/x86/vm/vm_version_x86.cpp | 5 +
src/cpu/zero/vm/vm_version_zero.cpp | 12 +-
src/cpu/zero/vm/vm_version_zero.hpp | 6 +-
src/share/vm/ci/ciInstanceKlass.cpp | 31 +-
src/share/vm/ci/ciInstanceKlass.hpp | 6 +-
src/share/vm/ci/ciMethod.cpp | 38 +
src/share/vm/ci/ciMethod.hpp | 2 +
src/share/vm/classfile/systemDictionary.cpp | 18 +-
src/share/vm/classfile/verifier.cpp | 28 +-
src/share/vm/classfile/vmSymbols.hpp | 2 +-
src/share/vm/compiler/compileBroker.cpp | 6 +-
src/share/vm/interpreter/bytecodeStream.cpp | 10 +-
src/share/vm/interpreter/bytecodeStream.hpp | 39 +-
src/share/vm/opto/bytecodeInfo.cpp | 44 +-
src/share/vm/opto/c2_globals.hpp | 13 +-
src/share/vm/opto/c2compiler.cpp | 9 +-
src/share/vm/opto/callGenerator.cpp | 62 +-
src/share/vm/opto/callGenerator.hpp | 1 +
src/share/vm/opto/callnode.cpp | 81 +-
src/share/vm/opto/callnode.hpp | 68 +-
src/share/vm/opto/cfgnode.cpp | 4 +-
src/share/vm/opto/chaitin.cpp | 5 +-
src/share/vm/opto/coalesce.cpp | 4 +-
src/share/vm/opto/compile.cpp | 64 +-
src/share/vm/opto/compile.hpp | 39 +-
src/share/vm/opto/doCall.cpp | 14 +-
src/share/vm/opto/escape.cpp | 80 +-
src/share/vm/opto/graphKit.cpp | 35 +-
src/share/vm/opto/ifnode.cpp | 2 +-
src/share/vm/opto/library_call.cpp | 4 +-
src/share/vm/opto/loopPredicate.cpp | 4 +-
src/share/vm/opto/macro.cpp | 95 +-
src/share/vm/opto/macro.hpp | 3 +-
src/share/vm/opto/matcher.cpp | 2 +
src/share/vm/opto/memnode.cpp | 644 ++++---
src/share/vm/opto/memnode.hpp | 6 +-
src/share/vm/opto/multnode.cpp | 33 +-
src/share/vm/opto/multnode.hpp | 2 +
src/share/vm/opto/node.cpp | 35 +-
src/share/vm/opto/node.hpp | 1 +
src/share/vm/opto/parse.hpp | 8 +-
src/share/vm/opto/parse1.cpp | 6 +-
src/share/vm/opto/parse2.cpp | 12 +-
src/share/vm/opto/parse3.cpp | 28 +-
src/share/vm/opto/parseHelper.cpp | 5 +
src/share/vm/opto/phase.cpp | 2 +
src/share/vm/opto/phase.hpp | 1 +
src/share/vm/opto/phaseX.cpp | 2 +-
src/share/vm/opto/phasetype.hpp | 8 +-
src/share/vm/opto/stringopts.cpp | 8 +-
src/share/vm/opto/type.cpp | 64 +-
src/share/vm/opto/type.hpp | 32 +-
src/share/vm/prims/unsafe.cpp | 32 +
src/share/vm/runtime/arguments.cpp | 26 +
src/share/vm/runtime/globals.hpp | 9 +-
src/share/vm/runtime/os.hpp | 2 +-
src/share/vm/runtime/vmStructs.cpp | 1 +
test/compiler/6934604/TestByteBoxing.java | 777 ++++++++++
test/compiler/6934604/TestDoubleBoxing.java | 777 ++++++++++
test/compiler/6934604/TestFloatBoxing.java | 777 ++++++++++
test/compiler/6934604/TestIntBoxing.java | 777 ++++++++++
test/compiler/6934604/TestLongBoxing.java | 777 ++++++++++
test/compiler/6934604/TestShortBoxing.java | 777 ++++++++++
test/compiler/codegen/IntRotateWithImmediate.java | 24 +-
test/compiler/stringopts/TestStringObjectInitialization.java | 78 +
test/compiler/unsafe/JdkInternalMiscUnsafeUnalignedAccess.java | 315 ++++
79 files changed, 6444 insertions(+), 582 deletions(-)
diffs (truncated from 9284 to 500 lines):
diff -r 5f3955f1fa41 -r e98d35509eaf .hgtags
--- a/.hgtags Wed Jun 01 02:06:55 2016 +0100
+++ b/.hgtags Wed Jul 20 05:26:25 2016 +0100
@@ -891,3 +891,5 @@
825fa447453ad85b3a6f11f87c5147b8b78fb3ab icedtea-2.6.6pre01
6e42747134be8a4a366d337da1fc84a847ad8381 jdk7u101-b00
3022a3d80efd705e861b90cece4f6fdc73f6de97 icedtea-2.6.6
+b4a17ff67e26e5e64680ab68c398dbecc46ee7c4 icedtea-2.6.7pre01
+14d0f4da4a74897fc3274f8f549f41544bb4625a jdk7u111-b00
diff -r 5f3955f1fa41 -r e98d35509eaf make/defs.make
--- a/make/defs.make Wed Jun 01 02:06:55 2016 +0100
+++ b/make/defs.make Wed Jul 20 05:26:25 2016 +0100
@@ -101,6 +101,18 @@
# hotspot version definitions
include $(GAMMADIR)/make/hotspot_version
+# When config parameter JDK_UPDATE_VERSION is defined,
+# Hotspot minor version should be set to that
+ifneq ($(JDK_UPDATE_VERSION),)
+ HS_MINOR_VER=$(JDK_UPDATE_VERSION)
+endif
+
+# When config parameter JDK_BUILD_NUMBER is defined,
+# Hotspot build number should be set to that
+ifneq ($(JDK_BUILD_NUMBER),)
+ HS_BUILD_NUMBER=$(subst b,,$(JDK_BUILD_NUMBER))
+endif
+
# Java versions needed
ifeq ($(PREVIOUS_JDK_VERSION),)
PREVIOUS_JDK_VERSION=$(JDK_PREVIOUS_VERSION)
diff -r 5f3955f1fa41 -r e98d35509eaf make/hotspot_version
--- a/make/hotspot_version Wed Jun 01 02:06:55 2016 +0100
+++ b/make/hotspot_version Wed Jul 20 05:26:25 2016 +0100
@@ -35,7 +35,7 @@
HS_MAJOR_VER=24
HS_MINOR_VER=95
-HS_BUILD_NUMBER=01
+HS_BUILD_NUMBER=00
JDK_MAJOR_VER=1
JDK_MINOR_VER=7
diff -r 5f3955f1fa41 -r e98d35509eaf make/linux/makefiles/gcc.make
--- a/make/linux/makefiles/gcc.make Wed Jun 01 02:06:55 2016 +0100
+++ b/make/linux/makefiles/gcc.make Wed Jul 20 05:26:25 2016 +0100
@@ -83,6 +83,7 @@
CFLAGS += $(LIBFFI_CFLAGS)
CFLAGS += $(LLVM_CFLAGS)
endif
+CFLAGS += -std=gnu++98
CFLAGS += $(VM_PICFLAG)
CFLAGS += -fno-rtti
CFLAGS += -fno-exceptions
@@ -93,6 +94,12 @@
ifneq "$(shell expr \( $(CC_VER_MAJOR) \> 4 \) \| \( \( $(CC_VER_MAJOR) = 4 \) \& \( $(CC_VER_MINOR) \>= 3 \) \))" "0"
CFLAGS += -fvisibility=hidden
endif
+# GCC 6 has more aggressive dead-store elimination which causes the VM to crash
+# It also optimises away null pointer checks which are still needed.
+# We turn both of these optimisations off.
+ifneq "$(shell expr \( $(CC_VER_MAJOR) \>= 6 \))" "0"
+CFLAGS += -fno-delete-null-pointer-checks -fno-lifetime-dse
+endif
ARCHFLAG = $(ARCHFLAG/$(BUILDARCH))
ARCHFLAG/i486 = -m32 -march=i586
diff -r 5f3955f1fa41 -r e98d35509eaf src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad Wed Jun 01 02:06:55 2016 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad Wed Jul 20 05:26:25 2016 +0100
@@ -9090,21 +9090,21 @@
%}
%}
-instruct rolI_rReg_Var_C_32(iRegLNoSp dst, iRegL src, iRegI shift, immI_32 c_32, rFlagsReg cr)
+instruct rolI_rReg_Var_C_32(iRegINoSp dst, iRegI src, iRegI shift, immI_32 c_32, rFlagsReg cr)
%{
match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c_32 shift))));
expand %{
- rolL_rReg(dst, src, shift, cr);
- %}
-%}
-
-instruct rolI_rReg_Var_C0(iRegLNoSp dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
+ rolI_rReg(dst, src, shift, cr);
+ %}
+%}
+
+instruct rolI_rReg_Var_C0(iRegINoSp dst, iRegI src, iRegI shift, immI0 c0, rFlagsReg cr)
%{
match(Set dst (OrI (LShiftI src shift) (URShiftI src (SubI c0 shift))));
expand %{
- rolL_rReg(dst, src, shift, cr);
+ rolI_rReg(dst, src, shift, cr);
%}
%}
@@ -9156,21 +9156,21 @@
%}
%}
-instruct rorI_rReg_Var_C_32(iRegLNoSp dst, iRegL src, iRegI shift, immI_32 c_32, rFlagsReg cr)
+instruct rorI_rReg_Var_C_32(iRegINoSp dst, iRegI src, iRegI shift, immI_32 c_32, rFlagsReg cr)
%{
match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c_32 shift))));
expand %{
- rorL_rReg(dst, src, shift, cr);
- %}
-%}
-
-instruct rorI_rReg_Var_C0(iRegLNoSp dst, iRegL src, iRegI shift, immI0 c0, rFlagsReg cr)
+ rorI_rReg(dst, src, shift, cr);
+ %}
+%}
+
+instruct rorI_rReg_Var_C0(iRegINoSp dst, iRegI src, iRegI shift, immI0 c0, rFlagsReg cr)
%{
match(Set dst (OrI (URShiftI src shift) (LShiftI src (SubI c0 shift))));
expand %{
- rorL_rReg(dst, src, shift, cr);
+ rorI_rReg(dst, src, shift, cr);
%}
%}
diff -r 5f3955f1fa41 -r e98d35509eaf src/cpu/aarch64/vm/assembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.cpp Wed Jun 01 02:06:55 2016 +0100
+++ b/src/cpu/aarch64/vm/assembler_aarch64.cpp Wed Jul 20 05:26:25 2016 +0100
@@ -1632,7 +1632,10 @@
Instruction_aarch64::extract(insn2, 4, 0)) {
// movk #imm16<<32
Instruction_aarch64::patch(branch + 4, 20, 5, (uint64_t)target >> 32);
- offset &= (1<<20)-1;
+ long dest = ((long)target & 0xffffffffL) | ((long)branch & 0xffff00000000L);
+ long pc_page = (long)branch >> 12;
+ long adr_page = (long)dest >> 12;
+ offset = adr_page - pc_page;
instructions = 2;
}
}
@@ -4920,11 +4923,12 @@
if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
_adrp(reg1, dest.target());
} else {
- unsigned long pc_page = (unsigned long)pc() >> 12;
- long offset = dest_page - pc_page;
- offset = (offset & ((1<<20)-1)) << 12;
- _adrp(reg1, pc()+offset);
- movk(reg1, ((unsigned long)dest.target() >> 32), 32);
+ unsigned long target = (unsigned long)dest.target();
+ unsigned long adrp_target
+ = (target & 0xffffffffUL) | ((unsigned long)pc() & 0xffff00000000UL);
+
+ _adrp(reg1, (address)adrp_target);
+ movk(reg1, target >> 32, 32);
}
byte_offset = (unsigned long)dest.target() & 0xfff;
}
diff -r 5f3955f1fa41 -r e98d35509eaf src/cpu/aarch64/vm/globals_aarch64.hpp
--- a/src/cpu/aarch64/vm/globals_aarch64.hpp Wed Jun 01 02:06:55 2016 +0100
+++ b/src/cpu/aarch64/vm/globals_aarch64.hpp Wed Jul 20 05:26:25 2016 +0100
@@ -48,11 +48,7 @@
// the the vep is aligned at CodeEntryAlignment whereas c2 only aligns
// the uep and the vep doesn't get real alignment but just slops on by
// only assured that the entry instruction meets the 5 byte size requirement.
-#ifdef COMPILER2
define_pd_global(intx, CodeEntryAlignment, 64);
-#else
-define_pd_global(intx, CodeEntryAlignment, 16);
-#endif // COMPILER2
define_pd_global(intx, OptoLoopAlignment, 16);
define_pd_global(intx, InlineFrequencyCount, 100);
diff -r 5f3955f1fa41 -r e98d35509eaf src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
--- a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp Wed Jun 01 02:06:55 2016 +0100
+++ b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp Wed Jul 20 05:26:25 2016 +0100
@@ -687,7 +687,7 @@
// count - element count
// tmp - scratch register
//
- // Destroy no registers!
+ // Destroy no registers except rscratch1 and rscratch2
//
void gen_write_ref_array_pre_barrier(Register addr, Register count, bool dest_uninitialized) {
BarrierSet* bs = Universe::heap()->barrier_set();
@@ -696,12 +696,13 @@
case BarrierSet::G1SATBCTLogging:
// With G1, don't generate the call if we statically know that the target in uninitialized
if (!dest_uninitialized) {
- __ push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
+ __ push_call_clobbered_registers();
if (count == c_rarg0) {
if (addr == c_rarg1) {
// exactly backwards!!
- __ stp(c_rarg0, c_rarg1, __ pre(sp, -2 * wordSize));
- __ ldp(c_rarg1, c_rarg0, __ post(sp, -2 * wordSize));
+ __ mov(rscratch1, c_rarg0);
+ __ mov(c_rarg0, c_rarg1);
+ __ mov(c_rarg1, rscratch1);
} else {
__ mov(c_rarg1, count);
__ mov(c_rarg0, addr);
@@ -711,7 +712,7 @@
__ mov(c_rarg1, count);
}
__ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_pre), 2);
- __ pop(RegSet::range(r0, r29), sp); // integer registers except lr & sp }
+ __ pop_call_clobbered_registers();
break;
case BarrierSet::CardTableModRef:
case BarrierSet::CardTableExtension:
@@ -742,7 +743,7 @@
case BarrierSet::G1SATBCTLogging:
{
- __ push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
+ __ push_call_clobbered_registers();
// must compute element count unless barrier set interface is changed (other platforms supply count)
assert_different_registers(start, end, scratch);
__ lea(scratch, Address(end, BytesPerHeapOop));
@@ -751,7 +752,7 @@
__ mov(c_rarg0, start);
__ mov(c_rarg1, scratch);
__ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_post), 2);
- __ pop(RegSet::range(r0, r29), sp); // integer registers except lr & sp }
+ __ pop_call_clobbered_registers();
}
break;
case BarrierSet::CardTableModRef:
@@ -811,7 +812,7 @@
assert_different_registers(s, d, count, rscratch1);
Label again, large, small;
- __ align(6);
+ __ align(CodeEntryAlignment);
__ bind(start);
__ cmp(count, 8);
__ br(Assembler::LO, small);
@@ -856,7 +857,7 @@
__ ret(lr);
- __ align(6);
+ __ align(CodeEntryAlignment);
__ bind(large);
// Fill 8 registers
@@ -1007,7 +1008,8 @@
}
// rscratch2 is the byte adjustment needed to align s.
__ cbz(rscratch2, aligned);
- __ lsr(rscratch2, rscratch2, exact_log2(granularity));
+ int shift = exact_log2(granularity);
+ if (shift) __ lsr(rscratch2, rscratch2, shift);
__ sub(count, count, rscratch2);
#if 0
@@ -1386,10 +1388,10 @@
// no-overlap entry point used by generate_conjoint_long_oop_copy().
//
address generate_disjoint_oop_copy(bool aligned, address *entry,
- const char *name, bool dest_uninitialized = false) {
+ const char *name, bool dest_uninitialized) {
const bool is_oop = true;
const size_t size = UseCompressedOops ? sizeof (jint) : sizeof (jlong);
- return generate_disjoint_copy(size, aligned, is_oop, entry, name);
+ return generate_disjoint_copy(size, aligned, is_oop, entry, name, dest_uninitialized);
}
// Arguments:
@@ -1404,10 +1406,11 @@
//
address generate_conjoint_oop_copy(bool aligned,
address nooverlap_target, address *entry,
- const char *name, bool dest_uninitialized = false) {
+ const char *name, bool dest_uninitialized) {
const bool is_oop = true;
const size_t size = UseCompressedOops ? sizeof (jint) : sizeof (jlong);
- return generate_conjoint_copy(size, aligned, is_oop, nooverlap_target, entry, name);
+ return generate_conjoint_copy(size, aligned, is_oop, nooverlap_target, entry,
+ name, dest_uninitialized);
}
@@ -1514,6 +1517,8 @@
}
#endif //ASSERT
+ gen_write_ref_array_pre_barrier(to, count, dest_uninitialized);
+
// save the original count
__ mov(count_save, count);
@@ -1655,9 +1660,11 @@
bool aligned = !UseCompressedOops;
StubRoutines::_arrayof_oop_disjoint_arraycopy
- = generate_disjoint_oop_copy(aligned, &entry, "arrayof_oop_disjoint_arraycopy");
+ = generate_disjoint_oop_copy(aligned, &entry, "arrayof_oop_disjoint_arraycopy",
+ /*dest_uninitialized*/false);
StubRoutines::_arrayof_oop_arraycopy
- = generate_conjoint_oop_copy(aligned, entry, &entry_oop_arraycopy, "arrayof_oop_arraycopy");
+ = generate_conjoint_oop_copy(aligned, entry, &entry_oop_arraycopy, "arrayof_oop_arraycopy",
+ /*dest_uninitialized*/false);
// Aligned versions without pre-barriers
StubRoutines::_arrayof_oop_disjoint_arraycopy_uninit
= generate_disjoint_oop_copy(aligned, &entry, "arrayof_oop_disjoint_arraycopy_uninit",
diff -r 5f3955f1fa41 -r e98d35509eaf src/cpu/aarch64/vm/templateTable_aarch64.cpp
--- a/src/cpu/aarch64/vm/templateTable_aarch64.cpp Wed Jun 01 02:06:55 2016 +0100
+++ b/src/cpu/aarch64/vm/templateTable_aarch64.cpp Wed Jul 20 05:26:25 2016 +0100
@@ -3087,7 +3087,7 @@
__ null_check(r0);
switch (state) {
case itos:
- __ ldr(r0, Address(r0, r1, Address::lsl(0)));
+ __ ldrw(r0, Address(r0, r1, Address::lsl(0)));
break;
case atos:
__ load_heap_oop(r0, Address(r0, r1, Address::lsl(0)));
@@ -3107,7 +3107,7 @@
__ ldrw(r3, Address(r2, in_bytes(constantPoolCacheOopDesc::base_offset() +
ConstantPoolCacheEntry::flags_offset())));
__ tbz(r3, ConstantPoolCacheEntry::is_volatile_shift, notVolatile);
- __ membar(MacroAssembler::LoadLoad);
+ __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
__ bind(notVolatile);
}
diff -r 5f3955f1fa41 -r e98d35509eaf src/cpu/aarch64/vm/vm_version_aarch64.cpp
--- a/src/cpu/aarch64/vm/vm_version_aarch64.cpp Wed Jun 01 02:06:55 2016 +0100
+++ b/src/cpu/aarch64/vm/vm_version_aarch64.cpp Wed Jul 20 05:26:25 2016 +0100
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2013, Red Hat Inc.
* Copyright (c) 1997, 2012, Oracle and/or its affiliates.
+ * Copyright (c) 2015, Red Hat Inc. All rights reserved.
* All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@@ -183,6 +183,12 @@
if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
UseCRC32Intrinsics = true;
}
+
+ // This machine allows unaligned memory accesses
+ if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
+ FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
+ }
+
#ifdef COMPILER2
if (FLAG_IS_DEFAULT(OptoScheduling)) {
OptoScheduling = true;
diff -r 5f3955f1fa41 -r e98d35509eaf src/cpu/ppc/vm/ppc.ad
--- a/src/cpu/ppc/vm/ppc.ad Wed Jun 01 02:06:55 2016 +0100
+++ b/src/cpu/ppc/vm/ppc.ad Wed Jul 20 05:26:25 2016 +0100
@@ -7653,7 +7653,7 @@
// SAPJVM GL 2013-10-29 Match ConvI2L(LoadI)
// Match loading integer and casting it to long.
-instruct loadI2L(iRegLdst dst, memory mem) %{
+instruct loadI2L(iRegLdst dst, memoryAlg4 mem) %{
match(Set dst (ConvI2L (LoadI mem)));
predicate(_kids[0]->_leaf->as_Load()->is_unordered());
ins_cost(MEMORY_REF_COST);
@@ -7665,7 +7665,7 @@
%}
// Match loading integer and casting it to long - acquire.
-instruct loadI2L_ac(iRegLdst dst, memory mem) %{
+instruct loadI2L_ac(iRegLdst dst, memoryAlg4 mem) %{
match(Set dst (ConvI2L (LoadI mem)));
ins_cost(3*MEMORY_REF_COST);
diff -r 5f3955f1fa41 -r e98d35509eaf src/cpu/ppc/vm/vm_version_ppc.cpp
--- a/src/cpu/ppc/vm/vm_version_ppc.cpp Wed Jun 01 02:06:55 2016 +0100
+++ b/src/cpu/ppc/vm/vm_version_ppc.cpp Wed Jul 20 05:26:25 2016 +0100
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2012, 2014 SAP AG. All rights reserved.
+ * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
+ * Copyright 2012, 2015 SAP AG. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -142,6 +142,11 @@
AllocatePrefetchStyle = 1; // Fall back if inappropriate.
assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
+
+ // This machine allows unaligned memory accesses
+ if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
+ FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
+ }
}
void VM_Version::print_features() {
diff -r 5f3955f1fa41 -r e98d35509eaf src/cpu/sparc/vm/vm_version_sparc.cpp
--- a/src/cpu/sparc/vm/vm_version_sparc.cpp Wed Jun 01 02:06:55 2016 +0100
+++ b/src/cpu/sparc/vm/vm_version_sparc.cpp Wed Jul 20 05:26:25 2016 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -274,6 +274,13 @@
if (!has_vis1()) // Drop to 0 if no VIS1 support
UseVIS = 0;
+ // This machine does not allow unaligned memory accesses
+ if (UseUnalignedAccesses) {
+ if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
+ warning("Unaligned memory access is not available on this CPU");
+ FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
+ }
+
#ifndef PRODUCT
if (PrintMiscellaneous && Verbose) {
tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
diff -r 5f3955f1fa41 -r e98d35509eaf src/cpu/x86/vm/vm_version_x86.cpp
--- a/src/cpu/x86/vm/vm_version_x86.cpp Wed Jun 01 02:06:55 2016 +0100
+++ b/src/cpu/x86/vm/vm_version_x86.cpp Wed Jul 20 05:26:25 2016 +0100
@@ -752,6 +752,11 @@
PrefetchFieldsAhead = prefetch_fields_ahead();
#endif
+ // This machine allows unaligned memory accesses
+ if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
+ FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
+ }
+
#ifndef PRODUCT
if (PrintMiscellaneous && Verbose) {
tty->print_cr("Logical CPUs per core: %u",
diff -r 5f3955f1fa41 -r e98d35509eaf src/cpu/zero/vm/vm_version_zero.cpp
--- a/src/cpu/zero/vm/vm_version_zero.cpp Wed Jun 01 02:06:55 2016 +0100
+++ b/src/cpu/zero/vm/vm_version_zero.cpp Wed Jul 20 05:26:25 2016 +0100
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
* Copyright 2009 Red Hat, Inc.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@@ -36,4 +36,12 @@
# include "os_bsd.inline.hpp"
#endif
-// This file is intentionally empty
+
+void VM_Version::initialize() {
+ get_processor_features();
+ // This machine does not allow unaligned memory accesses
+ if (! FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
+ warning("Unaligned memory access is not available on this CPU");
+ FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
+ }
+}
diff -r 5f3955f1fa41 -r e98d35509eaf src/cpu/zero/vm/vm_version_zero.hpp
--- a/src/cpu/zero/vm/vm_version_zero.hpp Wed Jun 01 02:06:55 2016 +0100
+++ b/src/cpu/zero/vm/vm_version_zero.hpp Wed Jul 20 05:26:25 2016 +0100
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2007 Red Hat, Inc.
+ * Copyright 2015 Red Hat, Inc.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -38,9 +38,7 @@
#endif
}
- static void initialize() {
- get_processor_features();
- }
+ static void initialize();
static const char* cpu_features() {
return "";
diff -r 5f3955f1fa41 -r e98d35509eaf src/share/vm/ci/ciInstanceKlass.cpp
--- a/src/share/vm/ci/ciInstanceKlass.cpp Wed Jun 01 02:06:55 2016 +0100
+++ b/src/share/vm/ci/ciInstanceKlass.cpp Wed Jul 20 05:26:25 2016 +0100
@@ -211,13 +211,42 @@
// ------------------------------------------------------------------
// ciInstanceKlass::uses_default_loader
-bool ciInstanceKlass::uses_default_loader() {
+bool ciInstanceKlass::uses_default_loader() const {
// Note: We do not need to resolve the handle or enter the VM
// in order to test null-ness.
return _loader == NULL;
}
// ------------------------------------------------------------------
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