/hg/release/icedtea7-forest-2.6/hotspot: 27 new changesets
andrew at icedtea.classpath.org
andrew at icedtea.classpath.org
Thu Mar 24 21:36:50 UTC 2016
changeset 545c9587b9b8 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=545c9587b9b8
author: goetz
date: Wed Feb 19 14:03:09 2014 -0800
8034797, PR2851: AIX: Fix os::naked_short_sleep() in os_aix.cpp after 8028280
Summary: imlements os::naked_short_sleep(jlong ms) on AIX
Reviewed-by: dholmes, kvn
changeset 2d1937a63be3 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=2d1937a63be3
author: mdoerr
date: Mon Oct 12 12:20:38 2015 +0200
8139421, PR2851: PPC64LE: MacroAssembler::bxx64_patchable kill register R12
Summary: Register R12 must be preserved for stub calls (e.g. deopt handler).
Reviewed-by: goetz
changeset 00d61f8f7506 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=00d61f8f7506
author: goetz
date: Tue Nov 17 08:59:21 2015 +0100
8139258, PR2851: PPC64LE: argument passing problem when passing 15 floats in native call
Reviewed-by: mdoerr, goetz
Contributed-by: asmundak at google.com
changeset ac019206b859 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=ac019206b859
author: enevill
date: Wed May 27 09:02:08 2015 +0000
8081289, PR2852: aarch64: add support for RewriteFrequentPairs in interpreter
Summary: Add support for RewriteFrequentPairs
Reviewed-by: roland
Contributed-by: alexander.alexeev at caviumnetworks.com
changeset dce66939c708 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=dce66939c708
author: enevill
date: Thu Jul 16 14:16:44 2015 +0000
8131483, PR2852: aarch64: illegal stlxr instructions
Summary: Do not generate stlxX with Ws == Xn
Reviewed-by: kvn, aph
changeset f1897ff27f48 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=f1897ff27f48
author: enevill
date: Tue Aug 18 12:40:22 2015 +0000
8133352, PR2852: aarch64: generates constrained unpredictable instructions
Summary: Fix generation of unpredictable STXR Rs, Rt, [Rn] with Rs == Rt
Reviewed-by: kvn, aph, adinn
changeset c350b120198a in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=c350b120198a
author: enevill
date: Thu Aug 20 09:40:08 2015 +0000
8133842, PR2852: aarch64: C2 generates illegal instructions with int shifts >=32
Summary: Fix logical operatations combined with shifts >= 32
Reviewed-by: duke
changeset 1af3458e9696 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=1af3458e9696
author: adinn
date: Wed Aug 26 17:13:59 2015 +0100
8134322, PR2852: AArch64: Fix several errors in C2 biased locking implementation
Summary: Several errors in C2 biased locking require fixing
Reviewed-by: kvn
Contributed-by: hui.shi at linaro.org
changeset fd049ef58ef4 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=fd049ef58ef4
author: enevill
date: Wed Sep 16 13:50:57 2015 +0000
8136615, PR2852: aarch64: elide DecodeN when followed by CmpP 0
Summary: remove DecodeN when comparing a narrow oop with 0
Reviewed-by: kvn, adinn
changeset 3bf69b02256f in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=3bf69b02256f
author: aph
date: Wed Sep 30 13:23:46 2015 +0000
8138641, PR2852: Disable C2 peephole by default for aarch64
Reviewed-by: roland
Contributed-by: felix.yang at linaro.org
changeset ec2870064132 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=ec2870064132
author: aph
date: Tue Sep 29 17:01:37 2015 +0000
8138575, PR2852: Improve generated code for profile counters
Reviewed-by: kvn
changeset 0df81d2a70a0 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=0df81d2a70a0
author: aph
date: Wed Nov 04 13:38:38 2015 +0100
8138966, PR2852: Intermittent SEGV running ParallelGC
Summary: Add necessary memory fences so that the parallel threads are unable to observe partially filled block tables.
Reviewed-by: tschatzl
changeset d4ac4e8e027e in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=d4ac4e8e027e
author: enevill
date: Thu Nov 19 15:15:20 2015 +0000
8143067, PR2852: aarch64: guarantee failure in javac
Summary: Fix adrp going out of range during code relocation
Reviewed-by: aph, kvn
changeset b2fa757283b4 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=b2fa757283b4
author: hshi
date: Tue Nov 24 09:02:26 2015 +0000
8143285, PR2852: aarch64: Missing load acquire when checking if ConstantPoolCacheEntry is resolved
Reviewed-by: roland, aph
changeset 2e9a8cdef031 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=2e9a8cdef031
author: enevill
date: Thu Dec 17 15:07:46 2015 +0000
PR2852: Add support for large code cache
Contributed-by: aph at redhat.com, edward.nevill at gmail.com
changeset 625f4b255e37 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=625f4b255e37
author: hshi
date: Thu Nov 26 15:37:04 2015 +0000
8143584, PR2852: Load constant pool tag and class status with load acquire
Reviewed-by: roland, aph
changeset d7d523e4201b in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=d7d523e4201b
author: aph
date: Wed Dec 16 11:35:59 2015 +0000
8144582, PR2852: AArch64 does not generate correct branch profile data
Reviewed-by: kvn
changeset a138d87cd91d in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=a138d87cd91d
author: fyang
date: Mon Dec 07 21:14:56 2015 +0800
8144201, PR2852: aarch64: jdk/test/com/sun/net/httpserver/Test6a.java fails with --enable-unlimited-crypto
Summary: Fix typo in stub generate_cipherBlockChaining_decryptAESCrypt
Reviewed-by: roland
changeset ee58cb062c75 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=ee58cb062c75
author: hshi
date: Wed Jan 20 04:56:51 2016 -0800
8147805, PR2852: aarch64: C1 segmentation fault due to inline Unsafe.getAndSetObject
Summary: In Aarch64 LIR_Assembler.atomic_op, keep stored data reference register in decompressed forms as it may be used later
Reviewed-by: aph
Contributed-by: hui.shi at linaro.org, felix.yang at linaro.org
changeset 40bf8942f743 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=40bf8942f743
author: enevill
date: Tue Jan 26 14:04:01 2016 +0000
8148240, PR2852: aarch64: random infrequent null pointer exceptions in javac
Summary: Disable fp as an allocatable register
Reviewed-by: aph
changeset abae0273d22b in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=abae0273d22b
author: aph
date: Mon Feb 29 10:42:55 2016 -0500
8146709, PR2852: AArch64: Incorrect use of ADRP for byte_map_base
changeset 231e593c3470 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=231e593c3470
author: andrew
date: Wed Mar 23 22:50:27 2016 +0000
PR2852: Apply ReservedCodeCacheSize default limiting to AArch64 only.
changeset 557b96c8b0fd in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=557b96c8b0fd
author: sgehwolf
date: Fri Dec 18 08:55:47 2015 +0100
6425769, PR2858: Allow specifying an address to bind JMX remote connector
Reviewed-by: jbachorik, dfuchs
changeset 631da593499e in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=631da593499e
author: sgehwolf
date: Fri Dec 18 08:55:47 2015 +0100
6425769: Allow specifying an address to bind JMX remote connector
Reviewed-by: jbachorik, dfuchs
changeset 73d541f0a08b in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=73d541f0a08b
author: andrew
date: Wed Mar 23 21:08:26 2016 +0000
Added tag jdk7u99-b00 for changeset 631da593499e
changeset 04d7046d2d41 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=04d7046d2d41
author: andrew
date: Thu Mar 24 01:02:33 2016 +0000
Merge jdk7u99-b00
changeset f614dcff9829 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=f614dcff9829
author: andrew
date: Thu Mar 24 21:35:21 2016 +0000
Added tag icedtea-2.6.5 for changeset 04d7046d2d41
diffstat:
.hgtags | 2 +
src/cpu/aarch64/vm/aarch64.ad | 177 ++--
src/cpu/aarch64/vm/aarch64_ad.m4 | 4 +-
src/cpu/aarch64/vm/assembler_aarch64.cpp | 389 +++++++--
src/cpu/aarch64/vm/assembler_aarch64.hpp | 104 +-
src/cpu/aarch64/vm/c1_CodeStubs_aarch64.cpp | 28 +-
src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp | 51 +-
src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.hpp | 8 +-
src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.cpp | 4 +-
src/cpu/aarch64/vm/c1_Runtime1_aarch64.cpp | 61 +-
src/cpu/aarch64/vm/c2_globals_aarch64.hpp | 2 +-
src/cpu/aarch64/vm/globalDefinitions_aarch64.hpp | 4 +
src/cpu/aarch64/vm/globals_aarch64.hpp | 9 +-
src/cpu/aarch64/vm/icBuffer_aarch64.cpp | 21 +-
src/cpu/aarch64/vm/interp_masm_aarch64.cpp | 12 +-
src/cpu/aarch64/vm/methodHandles_aarch64.cpp | 2 +-
src/cpu/aarch64/vm/nativeInst_aarch64.cpp | 141 ++-
src/cpu/aarch64/vm/nativeInst_aarch64.hpp | 74 +-
src/cpu/aarch64/vm/relocInfo_aarch64.cpp | 29 +-
src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp | 17 +-
src/cpu/aarch64/vm/stubGenerator_aarch64.cpp | 6 +-
src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp | 11 +-
src/cpu/aarch64/vm/templateTable_aarch64.cpp | 119 ++-
src/cpu/aarch64/vm/vm_version_aarch64.cpp | 4 +
src/cpu/aarch64/vm/vtableStubs_aarch64.cpp | 2 +-
src/cpu/ppc/vm/interpreter_ppc.cpp | 8 +
src/cpu/ppc/vm/macroAssembler_ppc.cpp | 8 -
src/cpu/ppc/vm/sharedRuntime_ppc.cpp | 19 +-
src/os/aix/vm/os_aix.cpp | 18 +-
src/os_cpu/linux_aarch64/vm/os_linux_aarch64.cpp | 9 +-
src/share/vm/code/compiledIC.cpp | 2 +-
src/share/vm/gc_implementation/parallelScavenge/psParallelCompact.hpp | 7 +-
src/share/vm/runtime/arguments.cpp | 6 +-
src/share/vm/services/diagnosticCommand.cpp | 6 +
src/share/vm/services/diagnosticCommand.hpp | 1 +
src/share/vm/utilities/globalDefinitions.hpp | 5 +
36 files changed, 946 insertions(+), 424 deletions(-)
diffs (truncated from 3213 to 500 lines):
diff -r 29cba58bd519 -r f614dcff9829 .hgtags
--- a/.hgtags Wed Jan 20 17:09:41 2016 +0000
+++ b/.hgtags Thu Mar 24 21:35:21 2016 +0000
@@ -886,3 +886,5 @@
c3cde6774003850aa6c44315c9c3e4dfdac69798 icedtea-2.6.3
b3c5ff648bcad305163b323ad15dde1b6234d501 jdk7u95-b00
19d919ae5506a750e3a0bcc6bd176c66b7e1e65d icedtea-2.6.4
+631da593499ee184ea8efb2bc5491e0d99ac636d jdk7u99-b00
+04d7046d2d41ae18c762fbdad7e114fdd55e2282 icedtea-2.6.5
diff -r 29cba58bd519 -r f614dcff9829 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad Wed Jan 20 17:09:41 2016 +0000
+++ b/src/cpu/aarch64/vm/aarch64.ad Thu Mar 24 21:35:21 2016 +0000
@@ -447,7 +447,7 @@
R26
/* R27, */ // heapbase
/* R28, */ // thread
- R29, // fp
+ /* R29, */ // fp
/* R30, */ // lr
/* R31 */ // sp
);
@@ -481,7 +481,7 @@
R26, R26_H,
/* R27, R27_H, */ // heapbase
/* R28, R28_H, */ // thread
- R29, R29_H, // fp
+ /* R29, R29_H, */ // fp
/* R30, R30_H, */ // lr
/* R31, R31_H */ // sp
);
@@ -775,16 +775,18 @@
int MachCallRuntimeNode::ret_addr_offset() {
// for generated stubs the call will be
- // bl(addr)
+ // far_call(addr)
// for real runtime callouts it iwll be
// mov(rscratch1, RuntimeAddress(addr)
// blrt rscratch1
CodeBlob *cb = CodeCache::find_blob(_entry_point);
if (cb) {
- return 4;
+ return MacroAssembler::far_branch_size();
} else {
// A 48-bit address. See movptr().
- return 16;
+ // then a blrt
+ // return 16;
+ return 4 * NativeInstruction::instruction_size;
}
}
@@ -1361,7 +1363,7 @@
uint size_java_to_interp()
{
// ob jdk7 we only need a mov oop and a branch
- return 2 * NativeInstruction::instruction_size;
+ return 7 * NativeInstruction::instruction_size;
}
// Offset from start of compiled java to interpreter stub to the load
@@ -1395,7 +1397,8 @@
// pool oop and GC overwrites the patch with movk/z 0x0000 again
__ movoop(rmethod, (jobject) NULL);
// This is recognized as unresolved by relocs/nativeinst/ic code
- __ b(__ pc());
+ __ movptr(rscratch1, 0);
+ __ br(rscratch1);
assert((__ offset() - offset) <= (int)size_java_to_interp(), "stub too big");
// Update current stubs pointer and restore insts_end.
@@ -1433,13 +1436,12 @@
// This is the unverified entry point.
MacroAssembler _masm(&cbuf);
- // no need to worry about 4-byte of br alignment on AArch64
__ cmp_klass(j_rarg0, rscratch2, rscratch1);
Label skip;
// TODO
// can we avoid this skip and still use a reloc?
__ br(Assembler::EQ, skip);
- __ b(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
+ __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
__ bind(skip);
}
@@ -1454,8 +1456,7 @@
uint size_exception_handler()
{
- // count up to 4 movz/n/k instructions and one branch instruction
- return 5 * NativeInstruction::instruction_size;
+ return MacroAssembler::far_branch_size();
}
// Emit exception handler code.
@@ -1470,7 +1471,7 @@
__ start_a_stub(size_exception_handler());
if (base == NULL) return 0; // CodeBuffer::expand failed
int offset = __ offset();
- __ b(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
+ __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
__ end_a_stub();
return offset;
@@ -1478,8 +1479,8 @@
uint size_deopt_handler()
{
- // count one adr and one branch instruction
- return 2 * NativeInstruction::instruction_size;
+ // count one adr and one far branch instruction
+ return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
}
// Emit deopt handler code.
@@ -1494,8 +1495,7 @@
int offset = __ offset();
__ adr(lr, __ pc());
- // should we load this into rscratch1 and use a br?
- __ b(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
+ __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
__ end_a_stub();
@@ -2583,16 +2583,7 @@
enc_class aarch64_enc_mov_byte_map_base(iRegP dst, immByteMapBase src) %{
MacroAssembler _masm(&cbuf);
- address page = (address)$src$$constant;
- Register dst_reg = as_Register($dst$$reg);
- unsigned long off;
- __ adrp(dst_reg, ExternalAddress(page), off);
- assert((off & 0x3ffL) == 0, "assumed offset aligned to 0x400");
- // n.b. intra-page offset will never change even if this gets
- // relocated so it is safe to omit the lea when off == 0
- if (off != 0) {
- __ lea(dst_reg, Address(dst_reg, off));
- }
+ __ load_byte_map_base($dst$$Register);
%}
enc_class aarch64_enc_mov_n(iRegN dst, immN src) %{
@@ -2802,11 +2793,11 @@
address addr = (address)$meth$$method;
if (!_method) {
// A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
- __ bl(Address(addr, relocInfo::runtime_call_type));
+ __ trampoline_call(Address(addr, relocInfo::runtime_call_type), &cbuf);
} else if (_optimized_virtual) {
- __ bl(Address(addr, relocInfo::opt_virtual_call_type));
+ __ trampoline_call(Address(addr, relocInfo::opt_virtual_call_type), &cbuf);
} else {
- __ bl(Address(addr, relocInfo::static_call_type));
+ __ trampoline_call(Address(addr, relocInfo::static_call_type), &cbuf);
}
if (_method) {
@@ -2818,22 +2809,19 @@
enc_class aarch64_enc_java_handle_call(method meth) %{
MacroAssembler _masm(&cbuf);
- // TODO fixme
- // this is supposed to preserve and restore SP around the call
- // need to check it works
+ // RFP is preserved across all calls, even compiled calls.
+ // Use it to preserve SP.
__ mov(rfp, sp);
address mark = __ pc();
address addr = (address)$meth$$method;
if (!_method) {
- // TODO check this
- // think we are calling generated Java here not x86
// A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
- __ bl(Address(addr, relocInfo::runtime_call_type));
+ __ trampoline_call(Address(addr, relocInfo::runtime_call_type), &cbuf);
} else if (_optimized_virtual) {
- __ bl(Address(addr, relocInfo::opt_virtual_call_type));
+ __ trampoline_call(Address(addr, relocInfo::opt_virtual_call_type), &cbuf);
} else {
- __ bl(Address(addr, relocInfo::static_call_type));
+ __ trampoline_call(Address(addr, relocInfo::static_call_type), &cbuf);
}
if (_method) {
@@ -2848,10 +2836,7 @@
enc_class aarch64_enc_java_dynamic_call(method meth) %{
MacroAssembler _masm(&cbuf);
address entry = (address)$meth$$method;
- RelocationHolder rh = virtual_call_Relocation::spec(__ pc());
- // we use movoop here as per emit_java_to_interp and c1's ic_call
- __ movoop(rscratch2, (jobject)Universe::non_oop_word(), /*immediate*/true);
- __ bl(Address(entry, rh));
+ __ ic_call(entry);
%}
enc_class aarch64_enc_call_epilog() %{
@@ -2872,7 +2857,7 @@
address entry = (address)$meth$$method;
CodeBlob *cb = CodeCache::find_blob(entry);
if (cb) {
- __ bl(Address(entry));
+ __ trampoline_call(Address(entry, relocInfo::runtime_call_type));
} else {
int gpcnt;
int fpcnt;
@@ -2885,7 +2870,7 @@
enc_class aarch64_enc_rethrow() %{
MacroAssembler _masm(&cbuf);
- __ b(RuntimeAddress(OptoRuntime::rethrow_stub()));
+ __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
%}
enc_class aarch64_enc_ret() %{
@@ -2930,12 +2915,12 @@
return;
}
- if (UseBiasedLocking) {
- __ biased_locking_enter(disp_hdr, oop, box, tmp, true, cont);
+ if (UseBiasedLocking && !UseOptoBiasInlining) {
+ __ biased_locking_enter(box, oop, disp_hdr, tmp, true, cont);
}
// Handle existing monitor
- if (EmitSync & 0x02) {
+ if ((EmitSync & 0x02) == 0) {
// we can use AArch64's bit test and branch here but
// markoopDesc does not define a bit index just the bit value
// so assert in case the bit pos changes
@@ -3075,7 +3060,7 @@
return;
}
- if (UseBiasedLocking) {
+ if (UseBiasedLocking && !UseOptoBiasInlining) {
__ biased_locking_exit(oop, tmp, cont);
}
@@ -7966,7 +7951,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8002,7 +7987,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8038,7 +8023,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8074,7 +8059,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8110,7 +8095,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8146,7 +8131,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8182,7 +8167,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8218,7 +8203,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8254,7 +8239,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8291,7 +8276,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8329,7 +8314,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8367,7 +8352,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8405,7 +8390,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8443,7 +8428,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8481,7 +8466,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8519,7 +8504,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8557,7 +8542,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8595,7 +8580,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8633,7 +8618,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8671,7 +8656,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8709,7 +8694,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8747,7 +8732,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8785,7 +8770,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::ASR,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8823,7 +8808,7 @@
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LSL,
- $src3$$constant & 0x3f);
+ $src3$$constant & 0x1f);
%}
ins_pipe(ialu_reg_reg_shift);
@@ -8866,8 +8851,8 @@
int s = 63 - lshift;
int r = (rshift - lshift) & 63;
__ sbfm(as_Register($dst$$reg),
- as_Register($src$$reg),
- r, s);
+ as_Register($src$$reg),
+ r, s);
%}
ins_pipe(ialu_reg_shift);
@@ -8889,8 +8874,8 @@
int s = 31 - lshift;
int r = (rshift - lshift) & 31;
__ sbfmw(as_Register($dst$$reg),
- as_Register($src$$reg),
- r, s);
+ as_Register($src$$reg),
+ r, s);
%}
ins_pipe(ialu_reg_shift);
@@ -8912,8 +8897,8 @@
int s = 63 - lshift;
int r = (rshift - lshift) & 63;
__ ubfm(as_Register($dst$$reg),
- as_Register($src$$reg),
- r, s);
+ as_Register($src$$reg),
+ r, s);
%}
ins_pipe(ialu_reg_shift);
@@ -8935,8 +8920,8 @@
int s = 31 - lshift;
int r = (rshift - lshift) & 31;
__ ubfmw(as_Register($dst$$reg),
- as_Register($src$$reg),
- r, s);
+ as_Register($src$$reg),
+ r, s);
%}
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