/hg/release/icedtea7-forest-2.6/hotspot: 18 new changesets
andrew at icedtea.classpath.org
andrew at icedtea.classpath.org
Thu Aug 3 16:19:58 UTC 2017
changeset e2b0fcea4493 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=e2b0fcea4493
author: andrew
date: Tue Aug 01 13:31:36 2017 +0100
Added tag icedtea-2.6.11pre01 for changeset a8044a7634d0
changeset 70191d4fad0c in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=70191d4fad0c
author: thartmann
date: Thu Mar 30 15:28:33 2017 +0200
8173770: Image conversion improvements
Reviewed-by: kvn, vlivanov, dlong, rhalade, mschoene, iignatyev
changeset 3a1e34513b37 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=3a1e34513b37
author: andrew
date: Wed Jul 26 19:57:31 2017 +0100
8179887: Build failure with glibc >= 2.24: error: 'int readdir_r(DIR*, dirent*, dirent**)' is deprecated
Summary: Disable deprecated declarations so the build doesn't fail with -Werror
Reviewed-by: omajid
changeset c2c1b068bd58 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=c2c1b068bd58
author: roland
date: Wed Jul 26 22:37:27 2017 +0100
8024069: replace_in_map() should operate on parent maps
Summary: type information gets lost because replace_in_map() doesn't update parent maps
Reviewed-by: kvn, twisti
changeset 0f18bae8b113 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=0f18bae8b113
author: roland
date: Wed Jul 26 23:35:36 2017 +0100
8026796: Make replace_in_map() on parent maps generic
Summary: propagate node replacements along control flow edges to callers
Reviewed-by: kvn, vlivanov
changeset d7dca9011eba in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=d7dca9011eba
author: vlivanov
date: Mon Jul 14 03:29:42 2014 -0700
8048703: ReplacedNodes dumps it's content to tty
Reviewed-by: roland, iveresov, drchase
changeset d7ea04813d4b in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=d7ea04813d4b
author: roland
date: Wed Feb 15 17:26:37 2017 -0800
8174164: SafePointNode::_replaced_nodes breaks with irreducible loops
Reviewed-by: kvn
changeset c511b66277fb in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=c511b66277fb
author: roland
date: Thu Feb 16 15:14:44 2017 -0800
8175097: [TESTBUG] 8174164 fix missed the test
Reviewed-by: kvn
changeset c3c450608912 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=c3c450608912
author: mdoerr
date: Fri Jun 02 08:45:34 2017 +0200
8181420: PPC: Image conversion improvements
Reviewed-by: thartmann, simonis, mbaesken
changeset 75662a7ec171 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=75662a7ec171
author: jvanek
date: Fri Jul 28 13:33:03 2017 +0100
8185502: No overflow operator on OpenJDK 7
Summary: Remove usage of overflow in x86_32.ad
Reviewed-by: roland, andrew
changeset 9c1a6eb49acb in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=9c1a6eb49acb
author: andrew
date: Tue Aug 01 14:12:31 2017 +0100
Added tag jdk7u151-b00 for changeset 75662a7ec171
changeset 2f25ab14c09e in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=2f25ab14c09e
author: andrew
date: Wed Aug 02 02:32:58 2017 +0100
Merge jdk7u151-b00
changeset ad21f8170b18 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=ad21f8170b18
author: aph
date: Wed Aug 02 08:41:53 2017 +0100
8144028, PR3431: Use AArch64 bit-test instructions in C2
Reviewed-by: kvn
changeset c8d9c145e76a in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=c8d9c145e76a
author: fyang
date: Wed Mar 23 18:00:46 2016 +0800
8152537, PR3431: aarch64: Make use of CBZ and CBNZ when comparing unsigned values with zero.
Summary: aarch64: c2 make use of CBZ and CBNZ when comparing unsigned values with zero.
Reviewed-by: aph
changeset dd276016c8d1 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=dd276016c8d1
author: roland
date: Tue Jul 04 21:23:37 2017 +0100
8183551, PR3431: AArch64: Image conversion improvements
changeset d0c7cea0660f in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=d0c7cea0660f
author: andrew
date: Thu Aug 03 07:27:30 2017 +0100
8185716: OpenJDK 7 PPC64 port uses a different ins_encode format in ppc.ad
Summary: Use existing ins_encode format for implementing 8181420
Reviewed-by: omajid
changeset 1396a255c595 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=1396a255c595
author: andrew
date: Thu Aug 03 07:27:59 2017 +0100
Added tag jdk7u151-b01 for changeset d0c7cea0660f
changeset 809ae803d8ea in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=809ae803d8ea
author: andrew
date: Thu Aug 03 17:03:28 2017 +0100
Merge jdk7u151-b01
diffstat:
.hgtags | 3 +
make/linux/makefiles/gcc.make | 1 +
src/cpu/aarch64/vm/aarch64.ad | 234 +++++++++++++++++++++++++++-
src/cpu/aarch64/vm/assembler_aarch64.hpp | 7 +-
src/cpu/ppc/vm/ppc.ad | 25 ++
src/cpu/sparc/vm/sparc.ad | 134 ++++++++++++++++
src/cpu/x86/vm/x86_32.ad | 150 +++++++++++++++++-
src/cpu/x86/vm/x86_64.ad | 42 +++++
src/share/vm/adlc/archDesc.cpp | 1 +
src/share/vm/opto/c2_globals.hpp | 2 +-
src/share/vm/opto/callGenerator.cpp | 11 +-
src/share/vm/opto/callnode.cpp | 1 +
src/share/vm/opto/callnode.hpp | 33 +++
src/share/vm/opto/classes.hpp | 1 +
src/share/vm/opto/compile.cpp | 9 +-
src/share/vm/opto/compile.hpp | 4 +-
src/share/vm/opto/graphKit.cpp | 43 ++++-
src/share/vm/opto/graphKit.hpp | 2 +-
src/share/vm/opto/ifnode.cpp | 2 +-
src/share/vm/opto/loopPredicate.cpp | 219 +++++++++++++++----------
src/share/vm/opto/loopnode.cpp | 4 +-
src/share/vm/opto/loopnode.hpp | 11 +-
src/share/vm/opto/loopopts.cpp | 4 +-
src/share/vm/opto/multnode.cpp | 57 ++++++
src/share/vm/opto/multnode.hpp | 8 +
src/share/vm/opto/node.cpp | 6 +
src/share/vm/opto/output.cpp | 1 +
src/share/vm/opto/parse.hpp | 5 +-
src/share/vm/opto/parse1.cpp | 27 +++-
src/share/vm/opto/replacednodes.cpp | 223 ++++++++++++++++++++++++++
src/share/vm/opto/replacednodes.hpp | 81 +++++++++
src/share/vm/opto/subnode.cpp | 54 ++++++
src/share/vm/opto/subnode.hpp | 9 +
src/share/vm/runtime/vmStructs.cpp | 1 +
src/share/vm/utilities/growableArray.hpp | 3 +-
test/compiler/c2/TestReplacedNodesOSR.java | 86 ++++++++++
test/compiler/codegen/8144028/BitTests.java | 164 +++++++++++++++++++
37 files changed, 1543 insertions(+), 125 deletions(-)
diffs (truncated from 2377 to 500 lines):
diff -r a8044a7634d0 -r 809ae803d8ea .hgtags
--- a/.hgtags Mon Jul 31 06:02:56 2017 +0100
+++ b/.hgtags Thu Aug 03 17:03:28 2017 +0100
@@ -906,3 +906,6 @@
22c5a6ca09e35b63baf51bad4cb3d8f0cf326705 jdk7u141-b01
56ad25be7d88c2c2da562fe1e8879c8723d01da1 jdk7u141-b02
8edec8d2933aa575e7da2656b0fc4d8b904b1997 icedtea-2.6.10
+a8044a7634d086a85ac71b8674b432424606a85c icedtea-2.6.11pre01
+75662a7ec1719b3133636d09bd078968579a55ab jdk7u151-b00
+d0c7cea0660f7a8188a7b8c1f6d1a6c8d6388fb0 jdk7u151-b01
diff -r a8044a7634d0 -r 809ae803d8ea make/linux/makefiles/gcc.make
--- a/make/linux/makefiles/gcc.make Mon Jul 31 06:02:56 2017 +0100
+++ b/make/linux/makefiles/gcc.make Thu Aug 03 17:03:28 2017 +0100
@@ -172,6 +172,7 @@
else
ACCEPTABLE_WARNINGS = -Wpointer-arith -Wconversion -Wsign-compare
endif
+ACCEPTABLE_WARNINGS += -Wno-deprecated-declarations
CFLAGS_WARN/DEFAULT = $(WARNINGS_ARE_ERRORS) $(ACCEPTABLE_WARNINGS)
# Special cases
diff -r a8044a7634d0 -r 809ae803d8ea src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad Mon Jul 31 06:02:56 2017 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad Thu Aug 03 17:03:28 2017 +0100
@@ -2439,7 +2439,6 @@
int disp = $mem$$disp;
if (index == -1) {
__ prfm(Address(base, disp), PSTL1KEEP);
- __ nop();
} else {
Register index_reg = as_Register(index);
if (disp == 0) {
@@ -10534,7 +10533,7 @@
ins_pipe(icmp_reg_reg);
%}
-instruct compL_reg_immI0(rFlagsReg cr, iRegL op1, immI0 zero)
+instruct compL_reg_immL0(rFlagsReg cr, iRegL op1, immL0 zero)
%{
match(Set cr (CmpL op1 zero));
@@ -10576,6 +10575,62 @@
ins_pipe(icmp_reg_imm);
%}
+instruct compUL_reg_reg(rFlagsRegU cr, iRegL op1, iRegL op2)
+%{
+ match(Set cr (CmpUL op1 op2));
+
+ effect(DEF cr, USE op1, USE op2);
+
+ ins_cost(INSN_COST);
+ format %{ "cmp $op1, $op2" %}
+
+ ins_encode(aarch64_enc_cmp(op1, op2));
+
+ ins_pipe(icmp_reg_reg);
+%}
+
+instruct compUL_reg_immL0(rFlagsRegU cr, iRegL op1, immL0 zero)
+%{
+ match(Set cr (CmpUL op1 zero));
+
+ effect(DEF cr, USE op1);
+
+ ins_cost(INSN_COST);
+ format %{ "tst $op1" %}
+
+ ins_encode(aarch64_enc_cmp_imm_addsub(op1, zero));
+
+ ins_pipe(icmp_reg_imm);
+%}
+
+instruct compUL_reg_immLAddSub(rFlagsRegU cr, iRegL op1, immLAddSub op2)
+%{
+ match(Set cr (CmpUL op1 op2));
+
+ effect(DEF cr, USE op1);
+
+ ins_cost(INSN_COST);
+ format %{ "cmp $op1, $op2" %}
+
+ ins_encode(aarch64_enc_cmp_imm_addsub(op1, op2));
+
+ ins_pipe(icmp_reg_imm);
+%}
+
+instruct compUL_reg_immL(rFlagsRegU cr, iRegL op1, immL op2)
+%{
+ match(Set cr (CmpUL op1 op2));
+
+ effect(DEF cr, USE op1);
+
+ ins_cost(INSN_COST * 2);
+ format %{ "cmp $op1, $op2" %}
+
+ ins_encode(aarch64_enc_cmp_imm(op1, op2));
+
+ ins_pipe(icmp_reg_imm);
+%}
+
instruct compP_reg_reg(rFlagsRegU cr, iRegP op1, iRegP op2)
%{
match(Set cr (CmpP op1 op2));
@@ -11054,6 +11109,181 @@
ins_pipe(pipe_cmp_branch);
%}
+instruct cmpUI_imm0_branch(cmpOpU cmp, iRegIorL2I op1, immI0 op2, label labl, rFlagsRegU cr) %{
+ match(If cmp (CmpU op1 op2));
+ predicate(n->in(1)->as_Bool()->_test._test == BoolTest::ne
+ || n->in(1)->as_Bool()->_test._test == BoolTest::eq
+ || n->in(1)->as_Bool()->_test._test == BoolTest::gt
+ || n->in(1)->as_Bool()->_test._test == BoolTest::le);
+ effect(USE labl);
+
+ ins_cost(BRANCH_COST);
+ format %{ "cbw$cmp $op1, $labl" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
+ if (cond == Assembler::EQ || cond == Assembler::LS)
+ __ cbzw($op1$$Register, *L);
+ else
+ __ cbnzw($op1$$Register, *L);
+ %}
+ ins_pipe(pipe_cmp_branch);
+%}
+
+instruct cmpUL_imm0_branch(cmpOpU cmp, iRegL op1, immL0 op2, label labl, rFlagsRegU cr) %{
+ match(If cmp (CmpUL op1 op2));
+ predicate(n->in(1)->as_Bool()->_test._test == BoolTest::ne
+ || n->in(1)->as_Bool()->_test._test == BoolTest::eq
+ || n->in(1)->as_Bool()->_test._test == BoolTest::gt
+ || n->in(1)->as_Bool()->_test._test == BoolTest::le);
+ effect(USE labl);
+
+ ins_cost(BRANCH_COST);
+ format %{ "cb$cmp $op1, $labl" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
+ if (cond == Assembler::EQ || cond == Assembler::LS)
+ __ cbz($op1$$Register, *L);
+ else
+ __ cbnz($op1$$Register, *L);
+ %}
+ ins_pipe(pipe_cmp_branch);
+%}
+
+// Test bit and Branch
+
+instruct cmpL_branch_sign(cmpOp cmp, iRegL op1, immL0 op2, label labl, rFlagsReg cr) %{
+ match(If cmp (CmpL op1 op2));
+ predicate(n->in(1)->as_Bool()->_test._test == BoolTest::lt
+ || n->in(1)->as_Bool()->_test._test == BoolTest::ge);
+ effect(USE labl);
+
+ ins_cost(BRANCH_COST);
+ format %{ "cb$cmp $op1, $labl # long" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
+ if (cond == Assembler::LT)
+ __ tbnz($op1$$Register, 63, *L);
+ else
+ __ tbz($op1$$Register, 63, *L);
+ %}
+ ins_pipe(pipe_cmp_branch);
+%}
+
+instruct cmpI_branch_sign(cmpOp cmp, iRegIorL2I op1, immI0 op2, label labl, rFlagsReg cr) %{
+ match(If cmp (CmpI op1 op2));
+ predicate(n->in(1)->as_Bool()->_test._test == BoolTest::lt
+ || n->in(1)->as_Bool()->_test._test == BoolTest::ge);
+ effect(USE labl);
+
+ ins_cost(BRANCH_COST);
+ format %{ "cb$cmp $op1, $labl # int" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
+ if (cond == Assembler::LT)
+ __ tbnz($op1$$Register, 31, *L);
+ else
+ __ tbz($op1$$Register, 31, *L);
+ %}
+ ins_pipe(pipe_cmp_branch);
+%}
+
+instruct cmpL_branch_bit(cmpOp cmp, iRegL op1, immL op2, immL0 op3, label labl, rFlagsReg cr) %{
+ match(If cmp (CmpL (AndL op1 op2) op3));
+ predicate((n->in(1)->as_Bool()->_test._test == BoolTest::ne
+ || n->in(1)->as_Bool()->_test._test == BoolTest::eq)
+ && is_power_of_2(n->in(2)->in(1)->in(2)->get_long()));
+ effect(USE labl);
+
+ ins_cost(BRANCH_COST);
+ format %{ "tb$cmp $op1, $op2, $labl" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
+ int bit = exact_log2($op2$$constant);
+ if (cond == Assembler::EQ)
+ __ tbz($op1$$Register, bit, *L);
+ else
+ __ tbnz($op1$$Register, bit, *L);
+ %}
+ ins_pipe(pipe_cmp_branch);
+%}
+
+instruct cmpI_branch_bit(cmpOp cmp, iRegIorL2I op1, immI op2, immI0 op3, label labl, rFlagsReg cr) %{
+ match(If cmp (CmpI (AndI op1 op2) op3));
+ predicate((n->in(1)->as_Bool()->_test._test == BoolTest::ne
+ || n->in(1)->as_Bool()->_test._test == BoolTest::eq)
+ && is_power_of_2(n->in(2)->in(1)->in(2)->get_int()));
+ effect(USE labl);
+
+ ins_cost(BRANCH_COST);
+ format %{ "tb$cmp $op1, $op2, $labl" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
+ int bit = exact_log2($op2$$constant);
+ if (cond == Assembler::EQ)
+ __ tbz($op1$$Register, bit, *L);
+ else
+ __ tbnz($op1$$Register, bit, *L);
+ %}
+ ins_pipe(pipe_cmp_branch);
+%}
+
+// Test bits
+
+instruct cmpL_and(cmpOp cmp, iRegL op1, immL op2, immL0 op3, rFlagsReg cr) %{
+ match(Set cr (CmpL (AndL op1 op2) op3));
+ predicate(Assembler::operand_valid_for_logical_immediate
+ (/*is_32*/false, n->in(1)->in(2)->get_long()));
+
+ ins_cost(INSN_COST);
+ format %{ "tst $op1, $op2 # long" %}
+ ins_encode %{
+ __ tst($op1$$Register, $op2$$constant);
+ %}
+ ins_pipe(ialu_reg_reg);
+%}
+
+instruct cmpI_and(cmpOp cmp, iRegIorL2I op1, immI op2, immI0 op3, rFlagsReg cr) %{
+ match(Set cr (CmpI (AndI op1 op2) op3));
+ predicate(Assembler::operand_valid_for_logical_immediate
+ (/*is_32*/true, n->in(1)->in(2)->get_int()));
+
+ ins_cost(INSN_COST);
+ format %{ "tst $op1, $op2 # int" %}
+ ins_encode %{
+ __ tstw($op1$$Register, $op2$$constant);
+ %}
+ ins_pipe(ialu_reg_reg);
+%}
+
+instruct cmpL_and_reg(cmpOp cmp, iRegL op1, iRegL op2, immL0 op3, rFlagsReg cr) %{
+ match(Set cr (CmpL (AndL op1 op2) op3));
+
+ ins_cost(INSN_COST);
+ format %{ "tst $op1, $op2 # long" %}
+ ins_encode %{
+ __ tst($op1$$Register, $op2$$Register);
+ %}
+ ins_pipe(ialu_reg_reg);
+%}
+
+instruct cmpI_and_reg(cmpOp cmp, iRegIorL2I op1, iRegIorL2I op2, immI0 op3, rFlagsReg cr) %{
+ match(Set cr (CmpI (AndI op1 op2) op3));
+
+ ins_cost(INSN_COST);
+ format %{ "tstw $op1, $op2 # int" %}
+ ins_encode %{
+ __ tstw($op1$$Register, $op2$$Register);
+ %}
+ ins_pipe(ialu_reg_reg);
+%}
+
+
// Conditional Far Branch
// Conditional Far Branch Unsigned
// TODO: fixme
diff -r a8044a7634d0 -r 809ae803d8ea src/cpu/aarch64/vm/assembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.hpp Mon Jul 31 06:02:56 2017 +0100
+++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp Thu Aug 03 17:03:28 2017 +0100
@@ -2459,8 +2459,11 @@
inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
- inline void tstw(Register Rd, unsigned imm) { andsw(zr, Rd, imm); }
- inline void tst(Register Rd, unsigned imm) { ands(zr, Rd, imm); }
+ inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
+ inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
+
+ inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
+ inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
diff -r a8044a7634d0 -r 809ae803d8ea src/cpu/ppc/vm/ppc.ad
--- a/src/cpu/ppc/vm/ppc.ad Mon Jul 31 06:02:56 2017 +0100
+++ b/src/cpu/ppc/vm/ppc.ad Thu Aug 03 17:03:28 2017 +0100
@@ -3498,6 +3498,14 @@
__ cmplwi(Rcrx, Rsrc1, Isrc2);
%}
+ enc_class enc_cmpldi(flagsReg crx, iRegIsrc src1, uimmL16 src2) %{
+ // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
+ MacroAssembler _masm(&cbuf);
+ Register Rsrc1 = reg_to_register_object($src1$$reg);
+ ConditionRegister Rcrx = reg_to_ConditionRegister_object($crx$$reg);
+ __ cmpldi(Rcrx, Rsrc1, $src2$$constant);
+ %}
+
enc_class enc_btst_reg(iRegIsrc src1, iRegIsrc src2) %{
// TODO: PPC port $archOpcode(ppc64Opcode_and_);
@@ -11356,6 +11364,23 @@
ins_pipe(pipe_class_compare);
%}
+// Added CmpUL for LoopPredicate.
+instruct cmpUL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
+ match(Set crx (CmpUL src1 src2));
+ format %{ "CMPLD $crx, $src1, $src2" %}
+ size(4);
+ ins_encode( enc_cmpld(crx, src1, src2) );
+ ins_pipe(pipe_class_compare);
+%}
+
+instruct cmpUL_reg_imm16(flagsReg crx, iRegLsrc src1, uimmL16 src2) %{
+ match(Set crx (CmpUL src1 src2));
+ format %{ "CMPLDI $crx, $src1, $src2" %}
+ size(4);
+ ins_encode( enc_cmpldi(crx, src1, src2) );
+ ins_pipe(pipe_class_compare);
+%}
+
instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
match(Set cr0 (CmpL (AndL src1 src2) zero));
// r0 is killed
diff -r a8044a7634d0 -r 809ae803d8ea src/cpu/sparc/vm/sparc.ad
--- a/src/cpu/sparc/vm/sparc.ad Mon Jul 31 06:02:56 2017 +0100
+++ b/src/cpu/sparc/vm/sparc.ad Thu Aug 03 17:03:28 2017 +0100
@@ -3448,6 +3448,16 @@
interface(CONST_INTER);
%}
+// Unsigned Long Immediate: 12-bit (non-negative that fits in simm13)
+operand immUL12() %{
+ predicate((0 <= n->get_long()) && (n->get_long() == (int)n->get_long()) && Assembler::is_simm13((int)n->get_long()));
+ match(ConL);
+ op_cost(0);
+
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
// Int Immediate non-negative
operand immU31()
%{
@@ -4064,6 +4074,15 @@
interface(REG_INTER);
%}
+// Condition Code Register, unsigned long comparisons.
+operand flagsRegUL() %{
+ constraint(ALLOC_IN_RC(int_flags));
+ match(RegFlags);
+
+ format %{ "xcc_UL" %}
+ interface(REG_INTER);
+%}
+
// Condition Code Register, floating comparisons, unordered same as "less".
operand flagsRegF() %{
constraint(ALLOC_IN_RC(float_flags));
@@ -8860,6 +8879,17 @@
ins_pipe(ialu_cconly_reg_reg);
%}
+instruct compUL_iReg(flagsRegUL xcc, iRegL op1, iRegL op2) %{
+ match(Set xcc (CmpUL op1 op2));
+ effect(DEF xcc, USE op1, USE op2);
+
+ size(4);
+ format %{ "CMP $op1,$op2\t! unsigned long" %}
+ opcode(Assembler::subcc_op3, Assembler::arith_op);
+ ins_encode(form3_rs1_rs2_rd(op1, op2, R_G0));
+ ins_pipe(ialu_cconly_reg_reg);
+%}
+
instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
match(Set icc (CmpI op1 op2));
effect( DEF icc, USE op1 );
@@ -8946,6 +8976,17 @@
ins_pipe(ialu_cconly_reg_imm);
%}
+instruct compUL_iReg_imm13(flagsRegUL xcc, iRegL op1, immUL12 op2) %{
+ match(Set xcc (CmpUL op1 op2));
+ effect(DEF xcc, USE op1, USE op2);
+
+ size(4);
+ format %{ "CMP $op1,$op2\t! unsigned long" %}
+ opcode(Assembler::subcc_op3, Assembler::arith_op);
+ ins_encode(form3_rs1_simm13_rd(op1, op2, R_G0));
+ ins_pipe(ialu_cconly_reg_imm);
+%}
+
// Compare Pointers
instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
match(Set pcc (CmpP op1 op2));
@@ -9312,6 +9353,44 @@
ins_pipe(cmp_br_reg_imm);
%}
+instruct cmpUL_reg_branch(cmpOpU cmp, iRegL op1, iRegL op2, label labl, flagsRegUL xcc) %{
+ match(If cmp (CmpUL op1 op2));
+ effect(USE labl, KILL xcc);
+
+ size(12);
+ ins_cost(BRANCH_COST);
+ format %{ "CMP $op1,$op2\t! unsigned long\n\t"
+ "BP$cmp $labl" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ Assembler::Predict predict_taken =
+ cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+ __ cmp($op1$$Register, $op2$$Register);
+ __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
+ __ delayed()->nop();
+ %}
+ ins_pipe(cmp_br_reg_reg);
+%}
+
+instruct cmpUL_imm_branch(cmpOpU cmp, iRegL op1, immL5 op2, label labl, flagsRegUL xcc) %{
+ match(If cmp (CmpUL op1 op2));
+ effect(USE labl, KILL xcc);
+
+ size(12);
+ ins_cost(BRANCH_COST);
+ format %{ "CMP $op1,$op2\t! unsigned long\n\t"
+ "BP$cmp $labl" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ Assembler::Predict predict_taken =
+ cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
+ __ cmp($op1$$Register, $op2$$constant);
+ __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
+ __ delayed()->nop();
+ %}
+ ins_pipe(cmp_br_reg_imm);
+%}
+
instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
match(If cmp (CmpL op1 op2));
effect(USE labl, KILL xcc);
@@ -9540,6 +9619,42 @@
ins_pipe(cbcond_reg_imm);
%}
+instruct cmpUL_reg_branch_short(cmpOpU cmp, iRegL op1, iRegL op2, label labl, flagsRegUL xcc) %{
+ match(If cmp (CmpUL op1 op2));
+ predicate(UseCBCond);
+ effect(USE labl, KILL xcc);
+
+ size(4);
+ ins_cost(BRANCH_COST);
+ format %{ "CXB$cmp $op1,$op2,$labl\t! unsigned long" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ assert(__ use_cbcond(*L), "back to back cbcond");
+ __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
+ %}
+ ins_short_branch(1);
+ ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
+ ins_pipe(cbcond_reg_reg);
+%}
+
+instruct cmpUL_imm_branch_short(cmpOpU cmp, iRegL op1, immL5 op2, label labl, flagsRegUL xcc) %{
+ match(If cmp (CmpUL op1 op2));
+ predicate(UseCBCond);
+ effect(USE labl, KILL xcc);
+
+ size(4);
+ ins_cost(BRANCH_COST);
+ format %{ "CXB$cmp $op1,$op2,$labl\t! unsigned long" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ assert(__ use_cbcond(*L), "back to back cbcond");
+ __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
+ %}
+ ins_short_branch(1);
+ ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
+ ins_pipe(cbcond_reg_imm);
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