/hg/icedtea8-forest/hotspot: 5 new changesets
andrew at icedtea.classpath.org
andrew at icedtea.classpath.org
Fri May 12 13:57:59 UTC 2017
changeset 9c14a73f419b in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=9c14a73f419b
author: adinn
date: Tue Mar 28 06:12:49 2017 -0400
8177661, PR3372: Correct ad rule output register types from iRegX to iRegXNoSp
Backport to jdk8 of JDK9 fix for JDK-8177661
changeset 0c2677696bae in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=0c2677696bae
author: aph
date: Tue Apr 04 14:49:03 2017 +0000
8173472, PR3372: AArch64: C1 comparisons with null only use 32-bit instructions
Reviewed-by: roland
changeset 75a52b17d004 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=75a52b17d004
author: njian
date: Sun Jan 22 16:33:54 2017 +0800
8172881, PR3372: AArch64: assertion failure: the int pressure is incorrect
Summary: Change the dst register type of get_and_setI/L/N/P from any register to non-special register.
Reviewed-by: aph
Contributed-by: yang.zhang at linaro.org
changeset d1ceb6c6cca9 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=d1ceb6c6cca9
author: aph
date: Tue Apr 04 14:59:08 2017 +0000
8170100, PR3372: AArch64: Crash in C1-compiled code accessing References
Reviewed-by: roland
changeset 00b7bbd261c9 in /hg/icedtea8-forest/hotspot
details: http://icedtea.classpath.org/hg/icedtea8-forest/hotspot?cmd=changeset;node=00b7bbd261c9
author: aph
date: Tue Apr 18 13:07:42 2017 -0300
8168699, PR3372: Validate special case invocations [AArch64 support]
diffstat:
src/cpu/aarch64/vm/aarch64.ad | 14 +++---
src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp | 45 ++++++++++++---------
src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp | 7 ++-
src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp | 6 +-
4 files changed, 41 insertions(+), 31 deletions(-)
diffs (181 lines):
diff -r a666b7151a84 -r 00b7bbd261c9 src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad Tue May 09 04:03:39 2017 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad Tue Apr 18 13:07:42 2017 -0300
@@ -9677,7 +9677,7 @@
%}
-instruct get_and_setI(indirect mem, iRegINoSp newv, iRegI prev) %{
+instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev) %{
match(Set prev (GetAndSetI mem newv));
format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
ins_encode %{
@@ -9686,7 +9686,7 @@
ins_pipe(pipe_serial);
%}
-instruct get_and_setL(indirect mem, iRegLNoSp newv, iRegL prev) %{
+instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev) %{
match(Set prev (GetAndSetL mem newv));
format %{ "atomic_xchg $prev, $newv, [$mem]" %}
ins_encode %{
@@ -9695,7 +9695,7 @@
ins_pipe(pipe_serial);
%}
-instruct get_and_setN(indirect mem, iRegNNoSp newv, iRegI prev) %{
+instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev) %{
match(Set prev (GetAndSetN mem newv));
format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
ins_encode %{
@@ -9704,7 +9704,7 @@
ins_pipe(pipe_serial);
%}
-instruct get_and_setP(indirect mem, iRegPNoSp newv, iRegP prev) %{
+instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev) %{
match(Set prev (GetAndSetP mem newv));
format %{ "atomic_xchg $prev, $newv, [$mem]" %}
ins_encode %{
@@ -15152,7 +15152,7 @@
%}
instruct string_indexof(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
- iRegI_R0 result, iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegI tmp4, rFlagsReg cr)
+ iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
%{
match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2,
@@ -15170,8 +15170,8 @@
%}
instruct string_indexof_con(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
- immI_le_4 int_cnt2, iRegI_R0 result, iRegI tmp1, iRegI tmp2,
- iRegI tmp3, iRegI tmp4, rFlagsReg cr)
+ immI_le_4 int_cnt2, iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,
+ iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
%{
match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1,
diff -r a666b7151a84 -r 00b7bbd261c9 src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Tue May 09 04:03:39 2017 +0100
+++ b/src/cpu/aarch64/vm/c1_LIRAssembler_aarch64.cpp Tue Apr 18 13:07:42 2017 -0300
@@ -1982,37 +1982,42 @@
}
if (opr2->is_constant()) {
+ bool is_32bit = false; // width of register operand
jlong imm;
+
switch(opr2->type()) {
+ case T_INT:
+ imm = opr2->as_constant_ptr()->as_jint();
+ is_32bit = true;
+ break;
case T_LONG:
- imm = opr2->as_constant_ptr()->as_jlong();
- break;
- case T_INT:
+ imm = opr2->as_constant_ptr()->as_jlong();
+ break;
case T_ADDRESS:
- imm = opr2->as_constant_ptr()->as_jint();
- break;
+ imm = opr2->as_constant_ptr()->as_jint();
+ break;
case T_OBJECT:
case T_ARRAY:
- imm = jlong(opr2->as_constant_ptr()->as_jobject());
- break;
+ imm = jlong(opr2->as_constant_ptr()->as_jobject());
+ break;
default:
- ShouldNotReachHere();
- break;
+ ShouldNotReachHere();
+ break;
}
if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
- if (type2aelembytes(opr1->type()) <= 4)
- __ cmpw(reg1, imm);
- else
- __ cmp(reg1, imm);
- return;
+ if (is_32bit)
+ __ cmpw(reg1, imm);
+ else
+ __ cmp(reg1, imm);
+ return;
} else {
- __ mov(rscratch1, imm);
- if (type2aelembytes(opr1->type()) <= 4)
- __ cmpw(reg1, rscratch1);
- else
- __ cmp(reg1, rscratch1);
- return;
+ __ mov(rscratch1, imm);
+ if (is_32bit)
+ __ cmpw(reg1, rscratch1);
+ else
+ __ cmp(reg1, rscratch1);
+ return;
}
} else
ShouldNotReachHere();
diff -r a666b7151a84 -r 00b7bbd261c9 src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp
--- a/src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp Tue May 09 04:03:39 2017 +0100
+++ b/src/cpu/aarch64/vm/c1_LIRGenerator_aarch64.cpp Tue Apr 18 13:07:42 2017 -0300
@@ -1224,12 +1224,17 @@
obj.load_item();
// info for exceptions
- CodeEmitInfo* info_for_exception = state_for(x);
+ CodeEmitInfo* info_for_exception =
+ (x->needs_exception_state() ? state_for(x) :
+ state_for(x, x->state_before(), true /*ignore_xhandler*/));
CodeStub* stub;
if (x->is_incompatible_class_change_check()) {
assert(patching_info == NULL, "can't patch this");
stub = new SimpleExceptionStub(Runtime1::throw_incompatible_class_change_error_id, LIR_OprFact::illegalOpr, info_for_exception);
+ } else if (x->is_invokespecial_receiver_check()) {
+ assert(patching_info == NULL, "can't patch this");
+ stub = new DeoptimizeStub(info_for_exception);
} else {
stub = new SimpleExceptionStub(Runtime1::throw_class_cast_exception_id, obj.result(), info_for_exception);
}
diff -r a666b7151a84 -r 00b7bbd261c9 src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp
--- a/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp Tue May 09 04:03:39 2017 +0100
+++ b/src/cpu/aarch64/vm/templateInterpreter_aarch64.cpp Tue Apr 18 13:07:42 2017 -0300
@@ -694,7 +694,7 @@
// and so we don't need to call the G1 pre-barrier. Thus we can use the
// regular method entry code to generate the NPE.
//
- // This code is based on generate_accessor_enty.
+ // This code is based on generate_accessor_entry.
//
// rmethod: Method*
// r13: senderSP must preserve for slow path, set SP to it on fast path
@@ -712,11 +712,11 @@
__ ldr(local_0, Address(esp, 0));
__ cbz(local_0, slow_path);
-
// Load the value of the referent field.
const Address field_address(local_0, referent_offset);
__ load_heap_oop(local_0, field_address);
+ __ mov(r19, r13); // Move senderSP to a callee-saved register
// Generate the G1 pre-barrier code to log the value of
// the referent field in an SATB buffer.
__ enter(); // g1_write may call runtime
@@ -728,7 +728,7 @@
true /* expand_call */);
__ leave();
// areturn
- __ andr(sp, r13, -16); // done with stack
+ __ andr(sp, r19, -16); // done with stack
__ ret(lr);
// generate a vanilla interpreter entry as the slow path
More information about the distro-pkg-dev
mailing list