/hg/release/icedtea7-forest-2.6/hotspot: 4 new changesets
andrew at icedtea.classpath.org
andrew at icedtea.classpath.org
Mon Nov 20 15:21:55 UTC 2017
changeset 3fa9788fa023 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=3fa9788fa023
author: dbuck
date: Fri Aug 11 23:51:07 2017 -0400
8185164, PR3433: GetOwnedMonitorInfo() returns incorrect owned monitor
Summary: The GetOwnedMonitorInfo() should not return a pending monitor
Reviewed-by: dcubed
changeset d48ba758f16d in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=d48ba758f16d
author: aph
date: Tue Aug 22 18:17:20 2017 +0100
8145438, PR3443, RH1482244: Guarantee failures since 8144028: Use AArch64 bit-test instructions in C2
Summary: Implement short and long versions of bit test instructions.
Reviewed-by: kvn
changeset 9777e52ab513 in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=9777e52ab513
author: kevinw
date: Wed Oct 25 17:09:59 2017 +0100
8138745, PR3465, RH1484399: Implement ExitOnOutOfMemory and CrashOnOutOfMemory in HotSpot
Reviewed-by: dholmes
Contributed-by: cheleswer.sahu at oracle.com
changeset a12bdfb01f6d in /hg/release/icedtea7-forest-2.6/hotspot
details: http://icedtea.classpath.org/hg/release/icedtea7-forest-2.6/hotspot?cmd=changeset;node=a12bdfb01f6d
author: andrew
date: Mon Nov 20 15:20:12 2017 +0000
Added tag icedtea-2.6.12pre01 for changeset 9777e52ab513
diffstat:
.hgtags | 1 +
src/cpu/aarch64/vm/aarch64.ad | 134 +++++++++++++++++-----
src/cpu/aarch64/vm/assembler_aarch64.hpp | 26 ++++
src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.hpp | 2 +
src/cpu/aarch64/vm/interp_masm_aarch64.cpp | 5 +-
src/share/vm/adlc/formssel.cpp | 3 +-
src/share/vm/runtime/globals.hpp | 7 +
src/share/vm/runtime/objectMonitor.cpp | 4 +-
src/share/vm/utilities/debug.cpp | 12 +-
9 files changed, 155 insertions(+), 39 deletions(-)
diffs (334 lines):
diff -r 3bcb98075200 -r a12bdfb01f6d .hgtags
--- a/.hgtags Thu Aug 10 06:31:31 2017 +0100
+++ b/.hgtags Mon Nov 20 15:20:12 2017 +0000
@@ -910,3 +910,4 @@
75662a7ec1719b3133636d09bd078968579a55ab jdk7u151-b00
d0c7cea0660f7a8188a7b8c1f6d1a6c8d6388fb0 jdk7u151-b01
809ae803d8ea9fd1af5cda606931959086dde30c icedtea-2.6.11
+9777e52ab513f7912e90433ccb6d7d6ecb7e0244 icedtea-2.6.12pre01
diff -r 3bcb98075200 -r a12bdfb01f6d src/cpu/aarch64/vm/aarch64.ad
--- a/src/cpu/aarch64/vm/aarch64.ad Thu Aug 10 06:31:31 2017 +0100
+++ b/src/cpu/aarch64/vm/aarch64.ad Mon Nov 20 15:20:12 2017 +0000
@@ -1540,10 +1540,14 @@
return 0;
}
-bool Matcher::is_short_branch_offset(int rule, int br_size, int offset)
-{
- Unimplemented();
- return false;
+// Is this branch offset short enough that a short branch can be used?
+//
+// NOTE: If the platform does not provide any short branch variants, then
+// this method should return false for offset 0.
+bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
+ // The passed offset is relative to address of the branch.
+
+ return (-32768 <= offset && offset < 32768);
}
const bool Matcher::isSimpleConstant64(jlong value) {
@@ -11153,7 +11157,8 @@
// Test bit and Branch
-instruct cmpL_branch_sign(cmpOp cmp, iRegL op1, immL0 op2, label labl, rFlagsReg cr) %{
+// Patterns for short (< 32KiB) variants
+instruct cmpL_branch_sign(cmpOp cmp, iRegL op1, immL0 op2, label labl) %{
match(If cmp (CmpL op1 op2));
predicate(n->in(1)->as_Bool()->_test._test == BoolTest::lt
|| n->in(1)->as_Bool()->_test._test == BoolTest::ge);
@@ -11163,16 +11168,15 @@
format %{ "cb$cmp $op1, $labl # long" %}
ins_encode %{
Label* L = $labl$$label;
- Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
- if (cond == Assembler::LT)
- __ tbnz($op1$$Register, 63, *L);
- else
- __ tbz($op1$$Register, 63, *L);
+ Assembler::Condition cond =
+ ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
+ __ tbr(cond, $op1$$Register, 63, *L);
%}
ins_pipe(pipe_cmp_branch);
-%}
-
-instruct cmpI_branch_sign(cmpOp cmp, iRegIorL2I op1, immI0 op2, label labl, rFlagsReg cr) %{
+ ins_short_branch(1);
+%}
+
+instruct cmpI_branch_sign(cmpOp cmp, iRegIorL2I op1, immI0 op2, label labl) %{
match(If cmp (CmpI op1 op2));
predicate(n->in(1)->as_Bool()->_test._test == BoolTest::lt
|| n->in(1)->as_Bool()->_test._test == BoolTest::ge);
@@ -11182,16 +11186,15 @@
format %{ "cb$cmp $op1, $labl # int" %}
ins_encode %{
Label* L = $labl$$label;
- Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
- if (cond == Assembler::LT)
- __ tbnz($op1$$Register, 31, *L);
- else
- __ tbz($op1$$Register, 31, *L);
+ Assembler::Condition cond =
+ ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
+ __ tbr(cond, $op1$$Register, 31, *L);
%}
ins_pipe(pipe_cmp_branch);
-%}
-
-instruct cmpL_branch_bit(cmpOp cmp, iRegL op1, immL op2, immL0 op3, label labl, rFlagsReg cr) %{
+ ins_short_branch(1);
+%}
+
+instruct cmpL_branch_bit(cmpOp cmp, iRegL op1, immL op2, immL0 op3, label labl) %{
match(If cmp (CmpL (AndL op1 op2) op3));
predicate((n->in(1)->as_Bool()->_test._test == BoolTest::ne
|| n->in(1)->as_Bool()->_test._test == BoolTest::eq)
@@ -11204,15 +11207,13 @@
Label* L = $labl$$label;
Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
int bit = exact_log2($op2$$constant);
- if (cond == Assembler::EQ)
- __ tbz($op1$$Register, bit, *L);
- else
- __ tbnz($op1$$Register, bit, *L);
+ __ tbr(cond, $op1$$Register, bit, *L);
%}
ins_pipe(pipe_cmp_branch);
-%}
-
-instruct cmpI_branch_bit(cmpOp cmp, iRegIorL2I op1, immI op2, immI0 op3, label labl, rFlagsReg cr) %{
+ ins_short_branch(1);
+%}
+
+instruct cmpI_branch_bit(cmpOp cmp, iRegIorL2I op1, immI op2, immI0 op3, label labl) %{
match(If cmp (CmpI (AndI op1 op2) op3));
predicate((n->in(1)->as_Bool()->_test._test == BoolTest::ne
|| n->in(1)->as_Bool()->_test._test == BoolTest::eq)
@@ -11225,10 +11226,79 @@
Label* L = $labl$$label;
Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
int bit = exact_log2($op2$$constant);
- if (cond == Assembler::EQ)
- __ tbz($op1$$Register, bit, *L);
- else
- __ tbnz($op1$$Register, bit, *L);
+ __ tbr(cond, $op1$$Register, bit, *L);
+ %}
+ ins_pipe(pipe_cmp_branch);
+ ins_short_branch(1);
+%}
+
+// And far variants
+instruct far_cmpL_branch_sign(cmpOp cmp, iRegL op1, immL0 op2, label labl) %{
+ match(If cmp (CmpL op1 op2));
+ predicate(n->in(1)->as_Bool()->_test._test == BoolTest::lt
+ || n->in(1)->as_Bool()->_test._test == BoolTest::ge);
+ effect(USE labl);
+
+ ins_cost(BRANCH_COST);
+ format %{ "cb$cmp $op1, $labl # long" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ Assembler::Condition cond =
+ ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
+ __ tbr(cond, $op1$$Register, 63, *L, /*far*/true);
+ %}
+ ins_pipe(pipe_cmp_branch);
+%}
+
+instruct far_cmpI_branch_sign(cmpOp cmp, iRegIorL2I op1, immI0 op2, label labl) %{
+ match(If cmp (CmpI op1 op2));
+ predicate(n->in(1)->as_Bool()->_test._test == BoolTest::lt
+ || n->in(1)->as_Bool()->_test._test == BoolTest::ge);
+ effect(USE labl);
+
+ ins_cost(BRANCH_COST);
+ format %{ "cb$cmp $op1, $labl # int" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ Assembler::Condition cond =
+ ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
+ __ tbr(cond, $op1$$Register, 31, *L, /*far*/true);
+ %}
+ ins_pipe(pipe_cmp_branch);
+%}
+
+instruct far_cmpL_branch_bit(cmpOp cmp, iRegL op1, immL op2, immL0 op3, label labl) %{
+ match(If cmp (CmpL (AndL op1 op2) op3));
+ predicate((n->in(1)->as_Bool()->_test._test == BoolTest::ne
+ || n->in(1)->as_Bool()->_test._test == BoolTest::eq)
+ && is_power_of_2(n->in(2)->in(1)->in(2)->get_long()));
+ effect(USE labl);
+
+ ins_cost(BRANCH_COST);
+ format %{ "tb$cmp $op1, $op2, $labl" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
+ int bit = exact_log2($op2$$constant);
+ __ tbr(cond, $op1$$Register, bit, *L, /*far*/true);
+ %}
+ ins_pipe(pipe_cmp_branch);
+%}
+
+instruct far_cmpI_branch_bit(cmpOp cmp, iRegIorL2I op1, immI op2, immI0 op3, label labl) %{
+ match(If cmp (CmpI (AndI op1 op2) op3));
+ predicate((n->in(1)->as_Bool()->_test._test == BoolTest::ne
+ || n->in(1)->as_Bool()->_test._test == BoolTest::eq)
+ && is_power_of_2(n->in(2)->in(1)->in(2)->get_int()));
+ effect(USE labl);
+
+ ins_cost(BRANCH_COST);
+ format %{ "tb$cmp $op1, $op2, $labl" %}
+ ins_encode %{
+ Label* L = $labl$$label;
+ Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
+ int bit = exact_log2($op2$$constant);
+ __ tbr(cond, $op1$$Register, bit, *L, /*far*/true);
%}
ins_pipe(pipe_cmp_branch);
%}
diff -r 3bcb98075200 -r a12bdfb01f6d src/cpu/aarch64/vm/assembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/assembler_aarch64.hpp Thu Aug 10 06:31:31 2017 +0100
+++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp Mon Nov 20 15:20:12 2017 +0000
@@ -2723,6 +2723,32 @@
void movptr(Register r, uintptr_t imm64);
+public:
+
+ // Generalized Test Bit And Branch, including a "far" variety which
+ // spans more than 32KiB.
+ void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
+ assert(cond == EQ || cond == NE, "must be");
+
+ if (far)
+ cond = ~cond;
+
+ void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
+ if (cond == Assembler::EQ)
+ branch = &Assembler::tbz;
+ else
+ branch = &Assembler::tbnz;
+
+ if (far) {
+ Label L;
+ (this->*branch)(Rt, bitpos, L);
+ b(dest);
+ bind(L);
+ } else {
+ (this->*branch)(Rt, bitpos, dest);
+ }
+ }
+
// macro instructions for accessing and updating floating point
// status register
//
diff -r 3bcb98075200 -r a12bdfb01f6d src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.hpp
--- a/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.hpp Thu Aug 10 06:31:31 2017 +0100
+++ b/src/cpu/aarch64/vm/c1_MacroAssembler_aarch64.hpp Mon Nov 20 15:20:12 2017 +0000
@@ -27,6 +27,8 @@
#ifndef CPU_AARCH64_VM_C1_MACROASSEMBLER_AARCH64_HPP
#define CPU_AARCH64_VM_C1_MACROASSEMBLER_AARCH64_HPP
+using MacroAssembler::null_check;
+
// C1_MacroAssembler contains high-level macros for C1
private:
diff -r 3bcb98075200 -r a12bdfb01f6d src/cpu/aarch64/vm/interp_masm_aarch64.cpp
--- a/src/cpu/aarch64/vm/interp_masm_aarch64.cpp Thu Aug 10 06:31:31 2017 +0100
+++ b/src/cpu/aarch64/vm/interp_masm_aarch64.cpp Mon Nov 20 15:20:12 2017 +0000
@@ -1370,9 +1370,8 @@
// the code to check if the event should be sent.
if (JvmtiExport::can_post_interpreter_events()) {
Label L;
- ldr(r3, Address(rthread, JavaThread::interp_only_mode_offset()));
- tst(r3, ~0);
- br(Assembler::EQ, L);
+ ldrw(r3, Address(rthread, JavaThread::interp_only_mode_offset()));
+ cbzw(r3, L);
call_VM(noreg, CAST_FROM_FN_PTR(address,
InterpreterRuntime::post_method_entry));
bind(L);
diff -r 3bcb98075200 -r a12bdfb01f6d src/share/vm/adlc/formssel.cpp
--- a/src/share/vm/adlc/formssel.cpp Thu Aug 10 06:31:31 2017 +0100
+++ b/src/share/vm/adlc/formssel.cpp Mon Nov 20 15:20:12 2017 +0000
@@ -1243,7 +1243,8 @@
!is_short_branch() && // Don't match another short branch variant
reduce_result() != NULL &&
strcmp(reduce_result(), short_branch->reduce_result()) == 0 &&
- _matrule->equivalent(AD.globalNames(), short_branch->_matrule)) {
+ _matrule->equivalent(AD.globalNames(), short_branch->_matrule) &&
+ equivalent_predicates(this, short_branch)) {
// The instructions are equivalent.
// Now verify that both instructions have the same parameters and
diff -r 3bcb98075200 -r a12bdfb01f6d src/share/vm/runtime/globals.hpp
--- a/src/share/vm/runtime/globals.hpp Thu Aug 10 06:31:31 2017 +0100
+++ b/src/share/vm/runtime/globals.hpp Mon Nov 20 15:20:12 2017 +0000
@@ -1247,6 +1247,13 @@
"in perm. This purely intended to allow debugging issues" \
"in production.") \
\
+ product(bool, ExitOnOutOfMemoryError, false, \
+ "JVM exits on the first occurrence of an out-of-memory error") \
+ \
+ product(bool, CrashOnOutOfMemoryError, false, \
+ "JVM aborts, producing an error log and core/mini dump, on the " \
+ "first occurrence of an out-of-memory error") \
+ \
/* tracing */ \
\
notproduct(bool, TraceRuntimeCalls, false, \
diff -r 3bcb98075200 -r a12bdfb01f6d src/share/vm/runtime/objectMonitor.cpp
--- a/src/share/vm/runtime/objectMonitor.cpp Thu Aug 10 06:31:31 2017 +0100
+++ b/src/share/vm/runtime/objectMonitor.cpp Mon Nov 20 15:20:12 2017 +0000
@@ -379,6 +379,8 @@
{ // Change java thread status to indicate blocked on monitor enter.
JavaThreadBlockedOnMonitorEnterState jtbmes(jt, this);
+ Self->set_current_pending_monitor(this);
+
DTRACE_MONITOR_PROBE(contended__enter, this, object(), jt);
if (JvmtiExport::should_post_monitor_contended_enter()) {
JvmtiExport::post_monitor_contended_enter(jt, this);
@@ -393,8 +395,6 @@
OSThreadContendState osts(Self->osthread());
ThreadBlockInVM tbivm(jt);
- Self->set_current_pending_monitor(this);
-
// TODO-FIXME: change the following for(;;) loop to straight-line code.
for (;;) {
jt->set_suspend_equivalent();
diff -r 3bcb98075200 -r a12bdfb01f6d src/share/vm/utilities/debug.cpp
--- a/src/share/vm/utilities/debug.cpp Thu Aug 10 06:31:31 2017 +0100
+++ b/src/share/vm/utilities/debug.cpp Mon Nov 20 15:20:12 2017 +0000
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -317,6 +317,16 @@
VMError err(message);
err.report_java_out_of_memory();
}
+
+ if (CrashOnOutOfMemoryError) {
+ tty->print_cr("Aborting due to java.lang.OutOfMemoryError: %s", message);
+ fatal(err_msg("OutOfMemory encountered: %s", message));
+ }
+
+ if (ExitOnOutOfMemoryError) {
+ tty->print_cr("Terminating due to java.lang.OutOfMemoryError: %s", message);
+ exit(3);
+ }
}
}
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