makeAddress and large frame sizes

[Tom Rodriguez]

> 
> Have you managed to not have any scratch registers?
> As I understand it (at least the convention I followed) the naming there is purely for "documentation" - basically those registers are guaranteed to not be in use at the start/end of a method so we can use them as scratch registers
> when setting up the stack, etc. But during normal codegen those two are just two normal registers.

C2 doesn’t mention r8 or r9 anywhere in aarch64.ad so they are definitely not allocatable registers there.  Also this comment indicates that C1 does the same:

// follow the C1 compiler in making registers
//
//   r0-r7,r10-r26 volatile (caller save)
//   r27-r32 system (no save, no allocate)
//   r8-r9 invisible to the allocator (so we can use them as scratch regs)

> 
> I guess the Aarch64 c1/2 uses scaled transfers as well - should probably raise the issue about the bailout in case of "offset >= 2^14" just for sanity though.
>  

It must be.  I think it may switch to the scaled mode based on the size of the operation down in Address::encode.  The encoding machinery in the aarch assembler is a bit hard to decode.  That’s some serious magic to bury that deep without some asserts too.

tom