hsail compiler emitting useless cvt instruction
Deneau, Tom
tom.deneau at amd.com
Wed Mar 19 22:39:11 UTC 2014
I noticed that in some cases our hsail codegen contains patterns like
cvt_s64_s32 $d4, $s1;
cvt_s64_s32 $d4, $d4;
I was surprised that the second cvt is legal hsail, but I guess for cvt, s32 can apply to a $d register.
(of course in this context it is useless).
We could ignore this in the Assembler but it would be nice to understand why it is happening.
What is a good way to find this out?
At least one place it seems to come from is the TypeCheck code that occurs when an object is stored into an array.
-- Tom
Here is from ciVisualizer after LIR generation
-1 v30|j = LOADCOMPRESSEDPOINTER long[v2|a + 8] v31|j kind: long shift: 3 base: 0 alignment: 3
-1 v32|j = LOAD long[v30|j + 232] kind: long
-1 v33|i = LOAD long[v32|j + 16] kind: int
-1 v34|j = CONVERT v33|i from: s32 to: s64
-1 v35|j = CONVERT v34|j from: s32 to: s64
-1 v36|j = LADD (x: v15|j, ~y: v35|j)
-1 v37|j = LOAD long[v36|j] kind: long
and after register number assignment
80 d2|j = LOADCOMPRESSEDPOINTER long[d1|a + 8] d4|j kind: long shift: 3 base: 0 alignment: 3
82 d2|j = LOAD long[d2|j + 232] kind: long
84 s1|i = LOAD long[d2|j + 16] kind: int
86 d4|j = CONVERT s1|i from: s32 to: s64
88 d4|j = CONVERT d4|j from: s32 to: s64
90 d5|j = LADD (x: d6|j, ~y: d4|j)
92 d4|j = LOAD long[d5|j] kind: long
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