hsail compiler emitting useless cvt instruction

[Tom Rodriguez]

The c1visualizer used to have both HIR and LIR in some of the views but that’s currently not working because of changes for the baseline compiler.  In the interim, if you have the latest bits, the first dump the c1visualizer gets should be called “After final schedule” which is a scheduled dump of the HIR.  The blocks should correspond to your LIR output so it should be easy to match them up.  Otherwise you can dump to IGV and try to find something that matches.

tom


On Mar 19, 2014, at 4:02 PM, Deneau, Tom <tom.deneau at amd.com> wrote:

> what is the best way to get the original IR?
> 
>> -----Original Message-----
>> From: Tom Rodriguez [mailto:tom.rodriguez at oracle.com]
>> Sent: Wednesday, March 19, 2014 5:54 PM
>> To: Deneau, Tom
>> Cc: graal-dev at openjdk.java.net
>> Subject: Re: hsail compiler emitting useless cvt instruction
>> 
>> Presumably it's there in your IR but it seems malformed to me.  The
>> second convert has a long input but it still thinks it's converting from
>> s32 to s64.  What's in the original IR?
>> 
>> tom
>> 
>> On Mar 19, 2014, at 3:39 PM, Deneau, Tom <tom.deneau at amd.com> wrote:
>> 
>>> I noticed that in some cases our hsail codegen contains patterns like
>>> 
>>>               cvt_s64_s32 $d4, $s1;
>>>               cvt_s64_s32 $d4, $d4;
>>> 
>>> I was surprised that the second cvt is legal hsail, but I guess for
>> cvt, s32 can apply to a $d register.
>>> (of course in this context it is useless).
>>> We could ignore this in the Assembler but it would be nice to
>> understand why it is happening.
>>> What is a good way to find this out?
>>> At least one place it seems to come from is the TypeCheck code that
>> occurs when an object is stored into an array.
>>> 
>>> -- Tom
>>> 
>>> Here is from ciVisualizer after LIR generation
>>> 
>>> -1      v30|j = LOADCOMPRESSEDPOINTER long[v2|a + 8] v31|j kind: long
>> shift: 3 base: 0 alignment: 3
>>> -1      v32|j = LOAD long[v30|j + 232] kind: long
>>> -1      v33|i = LOAD long[v32|j + 16] kind: int
>>> -1      v34|j = CONVERT v33|i from: s32 to: s64
>>> -1      v35|j = CONVERT v34|j from: s32 to: s64
>>> -1      v36|j = LADD (x: v15|j, ~y: v35|j)
>>> -1      v37|j = LOAD long[v36|j] kind: long
>>> 
>>> and after register number assignment
>>> 
>>> 80       d2|j = LOADCOMPRESSEDPOINTER long[d1|a + 8] d4|j kind: long
>> shift: 3 base: 0 alignment: 3
>>> 82       d2|j = LOAD long[d2|j + 232] kind: long
>>> 84       s1|i = LOAD long[d2|j + 16] kind: int
>>> 86       d4|j = CONVERT s1|i from: s32 to: s64
>>> 88       d4|j = CONVERT d4|j from: s32 to: s64
>>> 90       d5|j = LADD (x: d6|j, ~y: d4|j)
>>> 92       d4|j = LOAD long[d5|j] kind: long
>> 
> 
>