x86 FMA intrinsic support design

[Halimi, Jean-Philippe]

Hi all,

Thanks a lot for your feedback. It has been two weeks, and I have made some progress, however it looks like the design shared earlier is incomplete. From what I can see, there are a few classes missing in Graal to allow the implementation.

1. FusedMultiplyAddNode needs to extend a new TernaryNode.
2. AMD64ArithmeticLIRGenerator::emitFusedMultiplyAdd needs to be added, and I believe it needs a new AMD64Ternary class for code generation, to call the VexRVMOp.
	--> Here, I am not sure of whether AMD64Ternary is necessary, but I believe it is, since we are reading three values and writing back to the first one.

Do you believe this is the appropriate approach?

Thanks
-Jp

-----Original Message-----
From: graal-dev [mailto:graal-dev-bounces at openjdk.java.net] On Behalf Of Gilles Duboscq
Sent: Friday, March 29, 2019 2:34 AM
To: graal-dev at openjdk.java.net
Subject: Re: x86 FMA intrinsic support design

Hi Jean-Philippe,

That sounds like a good plan!

In terms of naming, i would call such a node `FusedMultiplyAddNode`: spelling out what it does is much more important than the fact that it comes from an intrinsic.

Thanks,
  Gilles

On 29/03/2019 01:04, Halimi, Jean-Philippe wrote:
> Hello,
> 
> I am currently looking into adding support for FMA intrinsics in Graal. I would like to share what I plan to do to make sure it is how it should be implemented.
> 
> 
> 1.       Add VexRVMOp class support in AMD64Assembler with the corresponding FMA instructions
> 
> a.       It requires to add the VexOpAssertion.FMA and CPUFeature.FMA flags
> 
> 2.       Add UseFMA flag from HotSpot flags in GraalHotSpotVMConfig.java
> 
> 3.       Add a registerFMA method in AMD64GraphBuilderPlugins::registerMathPlugins
> 
> a.       This requires to add a specific FMAIntrinsicNode, which will emit the corresponding FMA instructions.
> 
> Is there anything else that is needed in this case?
> 
> Thanks for your insights,
> Jp
>