RFR: 8352675: Support Intel AVX10 converged vector ISA feature detection [v9]

[Sandhya Viswanathan]

On Sat, 3 May 2025 07:28:04 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> src/hotspot/cpu/x86/vm_version_x86.cpp line 464:
>> 
>>> 462:     __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
>>> 463:     __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
>>> 464:     __ jccb(Assembler::equal, done); // jump if AVX is not supported
>> 
>> This doesn't not have same effect as before. Consider input is 0x10000000, the andl result will not be zero with this code and so jump to done will not happen. Whereas prior to this change, the cmpl with 0x18000000 will fail for equality and so a jump to done will happen.  This is the case for all the places where we are checking more than 1 set bit.
>
> Thanks @sviswa7 , sub-optimality was mainly around single-bit comparisons, where we could save redundant CMP after AND, and by flipping the predicate of subsequent flag-consuming JMP,  multibits compares should remain unaltered.

This and all the following places with multi-bit check still need to be fixed. If you walk through stock and new code in this PR when Address(rsi, 8) on line 468 has 0x10000000, you will observe that stock code will jump to done and new code will not jump to done. Let me know if I am missing something.

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PR Review Comment: https://git.openjdk.org/jdk/pull/24329#discussion_r2080592979