Request for reviews (M): 8004835: Improve AES intrinsics on x86

[Yasumasa Suenaga]

Hi Vladimir,

Source operand of Assembler::pshufb() seems to allow misaligned memory address.
Instruction reference of PSHUFB says following:

----------
When the source operand is a 128-bit memory operand, the operand must be aligned
on a 16-byte boundary or a general-protection exception (#GP) will be generated.
----------

Not only non-AVX but also AVX CPU needs 16-byte aligned memory address for source
operand of PSHUFB.
So I think that assert condition for AVX does not required in Assembler::pshufb() .

http://download.intel.com/products/processor/manual/325383.pdf


Thanks,

Yasumasa


On 2012/12/16 7:09, Vladimir Kozlov wrote:
> http://cr.openjdk.java.net/~kvn/8004835/webrev/
>
> Enable AES intrinsics on non-AVX cpus (Westmere), pshufb instruction in load_key() method could be used without AVX because it references only aligned memory "key_shuffle_mask".
>
> Group together aes instructions in encryptBlock/decryptBlock stubs as recommended by Intel Optimization Guide.
>
> Modified test/compiler/7184394 to test "ECB" mode.
>
> Ran compiler regression tests and jdk crypto and security tests with SunJCE default provider.
>
> Thanks,
> Vladimir