RFR (M) CR 8050147: StoreLoad barrier interferes with stack usages

[John Rose]

On Aug 11, 2014, at 1:18 AM, Aleksey Shipilev <aleksey.shipilev at oracle.com> wrote:

> The original experiment was taken without any knowledge if SP was
> aligned to >8 or not. If 8-byte read from SP(0) splits the cache line,
> then 8-byte read from SP(-CL) also splits the cache line *and* shares it
> with SP(0). Additional 8-byte push back was to dodge this. But, it
> appears the SP is aligned to 16 bytes?

That is true.  It is enforced and commented in several places, such as the definition 'StackAlignmentInBytes = 16'.

In any case, a native-size (8-byte, 64-bit)  read or write at SP(0) will never split a cache line, since that's where a 'call' instruction pushes the return pc, and we'd be badly broken if that did a split.

> If so, we can go with this:
> http://cr.openjdk.java.net/~shade/8050147/webrev.04/

Yes, please.

— John
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