RFR 8076276 support for AVX512

[Vladimir Kozlov]

I would suggest to remove MoveK and RegK from these changes since they are not used.
We can add them later when you have the use case.

sharedRuntime_x86_64.* You should have code and not comment:
// TODO: add ZMM save code

vm_version_x86.cpp Add code to verify that system preserve Z registers during interrupt. See code after comment :

// Some OSs have a bug when upper 128bits of YMM


I see repeated next pattern in C1 code. It should be moved to a function in FrameMap:

+        int num_caller_save_xmm_regs = FrameMap::nof_caller_save_xmm_regs;
+#if _LP64
+        if (UseAVX < 3) {
+          num_caller_save_xmm_regs = num_caller_save_xmm_regs / 2;
+        }
+#endif


In general we should avoid using #ifdef X86 in shared code: matcher.cpp. This file will not be issue if you remove RegK 
from changes.

c2compiler.cpp - can you move that code to Compile::pd_compiler2_init() which is platform specific?

matcher.cpp - typo 'eno':

+    // For VecZ we need eno alignment and 64 bytes (16 slots) for spills.


Thanks,
Vladimir


On 4/6/15 6:35 PM, Berg, Michael C wrote:
> Hi Folks,
>
> We (Intel) would like to contribute initial support for AVX512 (EVEX encoding, new register support, new ISA support,
> etc) for EVEX enabled microarchitectures.
> The contribution is referenced as Bug ID 8076276 as a performance enhancement.
>
> Please review this patch and comment as needed:
>
> Bug-id: https://bugs.openjdk.java.net/browse/JDK-8076276
>
> webrev:
> http://cr.openjdk.java.net/~kvn/8076276/webrev
>
> Superword optimizations covered on the vectorization path experience as much as 50% reduction in loop trace instruction
> count which make up the path length of EVEX encoded SIMD optimized loops.
>
> Vladimir Koslov has offered to sponsor this patch.
>