RFR 8076276 support for AVX512

[Vladimir Kozlov]

On 5/7/15 11:40 AM, Roland Westrelin wrote:
>>>> http://cr.openjdk.java.net/~kvn/8076276/webrev.02
>>>
>>> This looks good to me. A few minor remarks:
>>>
>>> Shouldn’t the #ifdef _LP64 new instruct be in x86_64.ad? I see there are already other #ifdef _LP64 in x86.ad so I’m not sure what the guideline is.
>>
>> Why you need #ifdef _LP64 in x86_64.ad were _LP64 is set by default (used only in 64-bit VM)? What new instructions you are talking about?
>
> I’m talking about:
> 4101 #ifdef _LP64
> 4102 instruct rvadd2L_reduction_reg(rRegL dst, rRegL src1, vecX src2, regF tmp, regF tmp2) %{
>
> for instance in x86.ad
> Why isn’t it in x86_64.ad?

I wanted to keep all vector instructions in one file. That is all.

Vladimir

>
> Roland.
>>
>>>
>>> In vm_version_x86.hpp, os_supports_avx_vectors(), you could have a single copy of the loop with different parameters.
>>>
>>> Not sure why you dropped:
>>>
>>> 3463 // Float register operands
>>> 3473 // Double register operands
>>>
>>> in x86_64.ad
>>>
>>> In chaitin.hpp:
>>>
>>> 144   uint16_t _num_regs;            // 2 for Longs and Doubles, 1 for all else
>>>
>>> comment is not aligned with the one below anymore.
>>>
>>> Roland.
>>>
>>
>> I also have questions to Michael.
>>
>> Why you renamed chunk2 to "alloc_class chunk3(RFLAGS);"?
>>
>> Why you moved "operand vecS() etc." from x86.ad ? Do you mean  evex is not supported in 32-bit?
>>
>> Thanks,
>> Vladimir
>