RFR 8076276 support for AVX512

[Vladimir Kozlov]

You did not answered my questions I think. Or I don't understand your 
answer:

 >> Why you renamed chunk2 to "alloc_class chunk3(RFLAGS);"?
 >>
 >> Why you moved "operand vecS() etc." from x86.ad ? Do you mean  evex 
is not supported in 32-bit?
 >>

And Roland's:

 >>> In vm_version_x86.hpp, os_supports_avx_vectors(), you could have a 
single copy of the loop with different parameters.

Thanks,
Vladimir

On 5/7/15 1:38 PM, Berg, Michael C wrote:
> Roland,
>
> For the usage of LP64 in the x86.ad file, I was following the existing examples, like replicate, which have specific forms for each type LONG usage, if applicable.
> I wanted to wait to add the 32-bit LONG versions of some of these macros (until later) as they expand to be larger than their 64-bit counterparts and are thought to be of lower performance.
> Currently we no make mention of vector instruction definitions outside of the x86.ad file definitions, so this is in keeping with both methods/attributes of instruction definition.
> New Instructions: The 64x2, 64x4, 32x4, 32x8 versions of extract/insert, kmov are all new.  There are new vector multiply instructions as well as extended forms that do not exist on earlier microarchitectures.
> See CPUID guards in the instruction definitions, there many that are AVX3 (UseAVX > 2) only for which are also evident in the assembler layer as supports_evex() instructions. This follows the current AVX512 ISA document in definition (available at: https://software.intel.com/en-us/isa-extensions .  By and large the assembler is now savy enough to encode all legacy x86 microarchitecture instructions, while supporting the new ones and the new encoding model.
>
> Thanks,
> Michael
>
> -----Original Message-----
> From: hotspot-compiler-dev [mailto:hotspot-compiler-dev-bounces at openjdk.java.net] On Behalf Of Roland Westrelin
> Sent: Thursday, May 07, 2015 11:40 AM
> To: Vladimir Kozlov
> Cc: hotspot-compiler-dev at openjdk.java.net
> Subject: Re: RFR 8076276 support for AVX512
>
>>>> http://cr.openjdk.java.net/~kvn/8076276/webrev.02
>>>
>>> This looks good to me. A few minor remarks:
>>>
>>> Shouldn't the #ifdef _LP64 new instruct be in x86_64.ad? I see there are already other #ifdef _LP64 in x86.ad so I'm not sure what the guideline is.
>>
>> Why you need #ifdef _LP64 in x86_64.ad were _LP64 is set by default (used only in 64-bit VM)? What new instructions you are talking about?
>
> I'm talking about:
> 4101 #ifdef _LP64
> 4102 instruct rvadd2L_reduction_reg(rRegL dst, rRegL src1, vecX src2, regF tmp, regF tmp2) %{
>
> for instance in x86.ad
> Why isn't it in x86_64.ad?
>
> Roland.
>>
>>>
>>> In vm_version_x86.hpp, os_supports_avx_vectors(), you could have a single copy of the loop with different parameters.
>>>
>>> Not sure why you dropped:
>>>
>>> 3463 // Float register operands
>>> 3473 // Double register operands
>>>
>>> in x86_64.ad
>>>
>>> In chaitin.hpp:
>>>
>>> 144   uint16_t _num_regs;            // 2 for Longs and Doubles, 1 for all else
>>>
>>> comment is not aligned with the one below anymore.
>>>
>>> Roland.
>>>
>>
>> I also have questions to Michael.
>>
>> Why you renamed chunk2 to "alloc_class chunk3(RFLAGS);"?
>>
>> Why you moved "operand vecS() etc." from x86.ad ? Do you mean  evex is not supported in 32-bit?
>>
>> Thanks,
>> Vladimir
>