8138894: C1: Support IRIW on weak memory platforms

[Lindenmaier, Goetz]

Hi Martin,

in c1_IR.hpp you have a cut&paste error:
void          set_wrote_volatile()             { _wrote_final = true; }
probably should set the new field _wrote_volatile.

Besides that the change looks good.  Reviewed.

Best regards,
  Goetz.


From: hotspot-compiler-dev [mailto:hotspot-compiler-dev-bounces at openjdk.java.net] On Behalf Of Doerr, Martin
Sent: Donnerstag, 8. Oktober 2015 23:44
To: hotspot compiler
Subject: 8138894: C1: Support IRIW on weak memory platforms

Hi,


Some time ago, we implemented support for ordering of "Independent Reads of Independent Writes" in the template interpreter and C2 Compiler for PPC64. However, it needs to be consistent with C1.



Without "IRIW" support, we generate load-acquire for volatile loads and release-store-fence for volatile stores.

With "IRIW" support, we generate fence-load-acquire for volatile loads and release-store for volatile stores.

CPU_NOT_MULTIPLE_COPY_ATOMIC is currently only defined on PPC64 (though it may be interesting for aarch64 as well).

This change is a prerequisite for our C1 on PPC64 contribution.



Webrev is here:

http://cr.openjdk.java.net/~mdoerr/8138894_c1_IRIW/webrev.00



Please review this change.  I need a sponsor, please.


Best regards,
  Martin

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