RFR: 8135157: DMB elimination in AArch64 C2 synchronization implementation

[Edward Nevill]

Hi Andrew

http://cr.openjdk.java.net/~aph/8135157-1

looks good but I think the following is incorrect in storeLConditional

-  ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval));
+  ins_encode(aarch64_enc_cmpxchg_acq(newval, heap_top_ptr));

I think the original line was correct in this case.

I will run it through jcstress on a selection of partner HW today.

All the best,
Ed.

On Mon, 2015-09-07 at 17:17 +0100, Andrew Haley wrote:
> Most of this patch is by Wei Tang of Linaro, and the explanation is in
> the bug report.  I have been over it fairly thoroughly because this is
> a very delicate and critical part of the compiler, and I think that
> Wei Tang's reasoning is correct.
> 
> I took the opportunity to cut out some dead wood because otherwise we
> would have had four almost-identical versions of cmpxchg.
> 
> OK?
> 
> Andrew.